US4773002A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprogram controller in which instruction following conditional branch instruction is selectively converted to a NOP instruction
Assignee: Hitachi Ltd
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Filing: 1986-05-21
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Granted: 1988-09-20
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Expires: 2006-05-21
Abstract
Abstract In a microprogram controller by pipeline control which includes a memory for storing a microprogram and a program counter for representing the address of the memory, a microprogram controller includes means for judging whether or not a branch condition of a branch microinstruction is satisfied and means for converting the microinstruction fetched from the memory to a NOP (No Operation) microinstruction from the output of the next step of the memory till the outputs after a plurality of steps by the affirmation output of the judging means. When the affirmation output is obtained from the judging means, part of the memory output is loaded into the program counter and when the negation output is obtained, a value as the sum of a current value plus 1 is loaded into the program counter.
Inventors
- 👤 Kazuhiko Iwasaki
- 👤 Noboru Yamaguchi
- 👤 Tsuneo Funabashi
- 👤 Junichi Tatezaki
- 👤 Takanori Shimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
229 words
A microprocessor comprising: a bus; a microprogram ROM coupled to said bus for storing microinstructions and for outputting said microinstructions to said bus, each of said microinstructions including first bit information which represents whether or not each of said microinstructions is a branch instruction, and each branch instruction including second bit information indicating whether said branch instruction is a conditional branch instruction or an unconditional branch instruction; an instruction decoder coupled to said bus for decoding a microinstruction received from said bus; an arithmetic unit responsive to said instruction decoder for executing a microinstruction and providing an information signal indicating whether or not a branch condition of a conditional branch instruction is satisfied; and microinstruction control means coupled to said bus and responsive to said first and second bit information for outputting a microinstruction from said microprogram ROM to said bus in response to a first clock pulse and for transmitting a microinstruction from said bus to said instruction decoder in response to a second clock pulse, and including microinstruction converting means responsive to said first clock pulse and to said information signal from said arithmetic unit for converting a microinstruction outputted to said bus in response to said first clock pulse to a no operation microinstruction when a branch condition of said conditional branch instruction has been satisfied as indicated by said information signal of said arithmetic unit.
Claim 2
Dependent Claim
229 words
A microprocessor comprising: a bus; a microprogram ROM coupled to said bus for storing microinstructions and for outputting said microinstructions to said bus, each of said microinstructions including first bit information which represents whether or not each of said microinstructions is a branch instruction, and each branch instruction including second bit information indicating whether said branch instruction is a conditional branch instruction or an unconditional branch instruction; an instruction decoder coupled to said bus for decoding a microinstruction received from said bus; an arithmetic unit responsive to said instruction decoder for executing a microinstruction and providing an information signal indicating whether or not a branch condition of a conditional branch instruction is satisfied; and microinstruction control means coupled to said bus and responsive to said first and second bit information for outputting a microinstruction from said microprogram ROM to said bus in response to a first clock pulse and for transmitting a microinstruction from said bus to said instruction decoder in response to a second clock pulse, and including microinstruction converting means responsive to said first clock pulse and to said information signal from said arithmetic unit for converting a microinstruction outputted to said bus in response to said first clock pulse to a no operation microinstruction when a branch condition of said conditional branch instruction has been satisfied as indicated by said information signal of said arithmetic unit.
Claim 3
Dependent Claim
25 words
A microprocessor according to claim 1, wherein said microprocessor is controlled by said first clock pulse and said second clock pulse in a pipeline manner.
Claim 4
Dependent Claim
87 words
A microprocessor according to claim 1, wherein said microinstruction converting means includes first means responsive to said second bit information from a branch instruction on said bus and said information signal from said arithmetic unit for producing an output signal indicating detection of an unconditional branch instruction or a conditional branch instruction whose branch condition has been satisfied, and second means connected to said bus and responsive to the output signal of said first means for converting a microinstruction on said bus to a no operation instruction.
Claim 5
Dependent Claim
98 words
A microprocess or according to claim 3, wherein said microinstruction control means further includes a program counter connected to said microprogram ROM for applying an address thereto in response to said first clock pulse, an incrementer connected to receive the output of said program counter, and multiplexer means responsive to the output signal of said first means for setting said program counter to an address included in a branch instruction on said bus and for setting said program counter in accordance with an output of said incrementer in the absence of said output signal of said first means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-20 | 1992-03-21 | 1992-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-20 | 1996-03-21 | 1996-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-20 | 2000-03-21 | 2000-09-20 | $7700.00 | Window Closed / Lapsed |