Patent US4779227A successfully refreshed from Google Patents.
US4779227A
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US
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1986-08-12
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Granted: 1988-10-18
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Expires: 2006-08-12
Abstract
Abstract A semiconductor memory device having data buses for connecting memory cells in memory cell arrays with input/output buffer circuit includes a plurality of memory cell arrays having repetitive patterns. In the device, a plurality of column decoders are adjacent to the memory cell arrays and have repetitive patterns. A portion of the column decoders is displaced from a regular location in the column decoder to a separate location on a substrate of the semiconductor memory device to leave a blank portion in the column decoder. The device also includes an input/output buffer circuit, data buses for connecting the memory cell arrays to the corresponding input/output buffer circuit through spaces outside the column decoders including the blank portion, and conductors for connecting the displaced portion of column decoders located in the separate location to the corresponding memory cell arrays through spaces outside the column decoders including the blank portion.
Inventors
- 👤 Setsuo Kurafuji
- 👤 Keizo Aoyama
- 👤 Hideo Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:40
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/10; G11C5/00; G11C5/02; G11C5/025; G11C8/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
205 words
A semiconductor memory device, comprising: a plurality of substantially parallel memory cell arrays, each memory cell array having a plurality of parallel columns, wherein said plurality of columns are regularly disposed at a first predetermined interval; a plurality of substantially parallel column decoder arrays, each column decoder array having a plurality of parallel column decoders, wherein said plurality of column decoders are regularly disposed at a second predetermined interval; a plurality of parallel data transfer means, each operatively coupled with a corresponding one of said plurality of columns, for transferring data from memory cells in said columns, each of said plurality of data transfer means being connected to a corresponding one of said column decoders; and a data bus means connected to said plurality of data transfer means, for communicating data between said memory cells of said columns and an input/output buffer circuit; wherein said first predetermined interval is larger than said second predetermined interval, and said plurality of memory arrays, said plurality of data transfer means, and said plurality of column decoders are respectively aligned in an end-to-end fashion, such that a space is formed between at least two adjacent column decoder arrays, and one of said data bus means extends in said space.
Claim 2
Dependent Claim
205 words
A semiconductor memory device, comprising: a plurality of substantially parallel memory cell arrays, each memory cell array having a plurality of parallel columns, wherein said plurality of columns are regularly disposed at a first predetermined interval; a plurality of substantially parallel column decoder arrays, each column decoder array having a plurality of parallel column decoders, wherein said plurality of column decoders are regularly disposed at a second predetermined interval; a plurality of parallel data transfer means, each operatively coupled with a corresponding one of said plurality of columns, for transferring data from memory cells in said columns, each of said plurality of data transfer means being connected to a corresponding one of said column decoders; and a data bus means connected to said plurality of data transfer means, for communicating data between said memory cells of said columns and an input/output buffer circuit; wherein said first predetermined interval is larger than said second predetermined interval, and said plurality of memory arrays, said plurality of data transfer means, and said plurality of column decoders are respectively aligned in an end-to-end fashion, such that a space is formed between at least two adjacent column decoder arrays, and one of said data bus means extends in said space.
Claim 3
Dependent Claim
14 words
A device according to claim 1, wherein said device has a single bit constitution.
Claim 4
Dependent Claim
18 words
A device according to claim 1, wherein said data bus means is composed of a single data bus.
Claim 5
Dependent Claim
25 words
A device according to claim 1, wherein said device is a dynamic random access memory and said data bus means is a single data bus.
Claim 6
Dependent Claim
36 words
A device according to claim 1, wherein each column decoder array is composed of a set of n column decoders for outputting a respective Y-direction address signal to a corresponding one of said data transfer means.
References Cited (Backward Citations)
US3936812A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-18 | 1992-04-18 | 1992-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-18 | 1996-04-18 | 1996-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-18 | 2000-04-18 | 2000-10-18 | $7700.00 | Window Closed / Lapsed |