Output current control circuit for reducing ground bounce noise

Claim 1

An output current control circuit for use with a CMOS output buffer for limiting the maximum output current thereof so as to reduce significantly ground bounce noise, said control circuit comprising in combination: an output stage formed of a pull-up transistor (P1) and a pull-down transistor (N1) connected together in series; said pull-up transistor (P1) having one of its main electrodes coupled to a first external power supply terminal (18), its other main electrode coupled to an output node (A), and its gate electrode connected to the output of a first drive source (14); said pull-down transistor (N1) having one of its main electrodes coupled to a second external power supply terminal (20), its other main electrode coupled to the output node (A), and its gate electrode coupled to the output of a second drive source (16); variable resistance means having a control line (34) for varying the resistance between said second drive source (16) and the gate electrode of said pull-down transistor (N1); and feedback means coupled between the gate electrode of said pull-down transistor (N1) and a separate system ground reference line (30) connected to said second external power supply terminal (20) for feeding back a reference voltage to the control line of said variable resistance means so as to vary the resistance and thus limit the output current, whereby the ground bounce noise at an internal ground potential node (E) connected between the source of said pull-down transistor and said second external power supply terminal is significantly reduced.