Patent US949331A successfully refreshed from Google Patents.
US4786830A
Expired / Lapsed
US
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CMOS input buffer circuit for TTL signals
Assignee: US Philips Corp
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Filing: 1987-06-22
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Granted: 1988-11-22
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Expires: 2007-06-22
Abstract
Abstract A TTL to CMOS-input buffer has minimal sensitivity of threshold level variation with changes in device parameters. In particular, the design is insensitive to P-channel characteristics over very wide ranges of transistor threshold voltages and gain parameter spreads.
Inventors
- 👤 Richard C. Foss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:57
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
139 words
A CMOS-input circuit, which includes an input CMOS-inverter having a PMOS-switch transistor and an NMOS-load transistor, wherein the conductive channel of the PMOS-switch transistor is connected in series with said NMOS-load transistor between an output node and a first power supply terminal, the NMOS-load transistor substantially defines the load current when the PMOS-switch transistor is conductive, a further NMOS-transistor, an NMOS-transistor of the input inverter being connected to a second power supply terminal via said further NMOS-transistor, the gate of said further transistor being connected to the input of the input inverter, a feedback transistor device, the common node of the NMOS-transistor of the input inverter and of the further NMOS-transistor being connected by said feedback transistor device to the first power supply terminal, and the feedback transistor device being controlled by the output signal of the input inverter.
Claim 2
Dependent Claim
139 words
A CMOS-input circuit, which includes an input CMOS-inverter having a PMOS-switch transistor and an NMOS-load transistor, wherein the conductive channel of the PMOS-switch transistor is connected in series with said NMOS-load transistor between an output node and a first power supply terminal, the NMOS-load transistor substantially defines the load current when the PMOS-switch transistor is conductive, a further NMOS-transistor, an NMOS-transistor of the input inverter being connected to a second power supply terminal via said further NMOS-transistor, the gate of said further transistor being connected to the input of the input inverter, a feedback transistor device, the common node of the NMOS-transistor of the input inverter and of the further NMOS-transistor being connected by said feedback transistor device to the first power supply terminal, and the feedback transistor device being controlled by the output signal of the input inverter.
Claim 3
Dependent Claim
56 words
A CMOS-input circuit as claimed in claim 1, characterized in that the output of the input inverter is connected to the input of a first inverter circuit, the output of which is connected to an input of a second inverter circuit, of which the output is connected to a control input of the feedback transistor device.
Claim 4
Dependent Claim
16 words
A CMOS-input circuit as claimed in claim 2, characterized in that the inverter circuits are CMOS-inverters.
Claim 5
Dependent Claim
25 words
A CMOS-circuit as claimed in claim 1, characterized in that the feedback transistor device comprises two NMOS-transistors in series, the gates of which are interconnected.
Claim 6
Dependent Claim
54 words
A CMOS-input circuit as claimed in claim 3, characterized in that the PMOS-transistor of the first inverter is connected to the first power supply terminal via an NMOS-transistor device, which is connected as a diode, and via a PMOS-transistor device, the gate electrode of which is connected to the output of the second inverter.
Claim 7
Dependent Claim
32 words
A CMOS-input circuit as claimed in claim 3 or 5, characterized in that the PMOS-transistor of the first inverter has substantially the same width/length-ratio as the PMOS transistor of the input inverter.
Claim 8
Dependent Claim
31 words
A CMOS-input circuit as claimed in claim 1, characterized in that the width/length ratio of the NMOS-load transistor is at most one fifth times the width/length ratio of the PMOS-switch transistor.
Claim 9
Dependent Claim
23 words
A CMOS-input circuit as claimed in claim 1, characterized in that the NMOS-load transistor is an NMOS-transistor which is connected as a diode.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-22 | 1992-05-23 | 1992-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-22 | 1996-05-23 | 1996-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-22 | 2000-05-23 | 2000-11-22 | $7700.00 | Window Closed / Lapsed |