Abstract A counter circuit for counting pulses inputted thereto asynchronously during a fixed period includes a counter 12' for counting the input pulses, a register 13 for storing pulses outputted by the counter 12' at fixed periods, and a control circuit 11' for generating a signal that controls the operating state of the counter 12' and register 13. When a signal that decides the operating period of the counter 12' is not being generated, namely between pulses indicative of the operating period, the counter 12' performs an ordinary counting operation. If an input pulse for counting is applied to the counter 12' during a period of time in which the abovementioned pulse is being generated, the control circuit 11' causes the counting operation to continue without clearing the counted value in the counter 12', after which the counted value in counter 12' is outputted to the register 13 to be latched therein, thereby preventing miscounting in the register 13.
A counter circuit for counting input pulses inputted thereto asynchronously during a fixed period and storing the number of counted pulses in a register, comprising: means for counting input pulses generated during a fixed period; means for generating a first pulse to latch a value counted by said counting means in the register, to clear said counting means and to start a new fixed period; means for causing the counting operation to continue without clearing said counted value from said counting means when an input pulse is applied during generation of said first pulse, so that said input pulse is counted; and means for latching the counted value in the register and clearing the counted value from said counting means after said input pulse is counted.
Claim 2
Dependent Claim
126 words
A counter circuit for counting input pulses inputted thereto asynchronously during a fixed period and storing the number of counted pulses in a register, comprising: means for counting input pulses generated during a fixed period; means for generating a first pulse to latch a value counted by said counting means in the register, to clear said counting means and to start a new fixed period; means for causing the counting operation to continue without clearing said counted value from said counting means when an input pulse is applied during generation of said first pulse, so that said input pulse is counted; and means for latching the counted value in the register and clearing the counted value from said counting means after said input pulse is counted.
Claim 3
Dependent Claim
15 words
A counter circuit according to claim 1, wherein said counting means is an up/down counter.
Claim 4
Dependent Claim
21 words
A counter circuit according to claim 1, wherein said asynchronously inputted input signals are pulses from a numerically controlled servo circuit.
Claim 5
Dependent Claim
21 words
A counter circuit according to claim 2, wherein said asynchronously inputted input signals are pulses from a numerically controlled servo circuit.