Watchdog timer having a reset detection circuit

Claim 2

A watchdog timer comprising a reset data detection circuit for detecting input reset data and outputting a reset signal, and a first counter that outputs a carry signal unless, before its count overflows, it receives a reset signal from said reset data detection circuit, wherein said reset data detection circuit comprises: a latch circuit for latching said reset data, a second counter for counting the number of times a said reset signal is generated, and a comparator for comparing the output data from said latch circuit and said second counter and outputting said reset signal when the output data from said latch circuit and the output data from said second counter match.

Claim 3

A watchdog timer according to claim 1, wherein the latch circuit is connected to receive data from a data bus and latches the date upon receipt of a timer write signal which is supplied from the outside.

Claim 4

A watchdog timer according to claim 1, wherein the first counter receives and counts clock pulses which are periodically produced.

Claim 5

A watchdog timer according to claim 1, wherein the first counter starts counting up from 0 when it is reset.

Claim 6

A watchdog timer according to claim 1, further comprising a differentiating circuit receiving the output of the comparator and producing a pulse in synchronism with a clock, and wherein the output of the differentiating circuit is applied to said first counter to reset it and to said second counter to increment it.

Claim 7

A combination of a CPU and a watchdog timer, the watchdog timer comprising a reset data detection circuit for detecting input reset data and outputting a reset signal, and a first counter that outputs a carry signal unless, before its count overflows, it receives a reset signal from said reset data detection circuit, wherein said reset data detection circuit comprises: a latch circuit for latching said reset data, a second counter for counting the number of times said reset signal is generated, and a comparator for comparing the output data from said latch circuit and said second counter and outputting said reset signal when the output data from said latch circuit and the output data from said second counter match, and the CPU is programmed to execute instructions for writing reset data into the latch circuit, the data written into the latch circuit correspondingly incrementing by 1 said second counter each time one of said instructions for writing the reset data is executed.

Claim 8

A combination of a CPU and a watchdog timer, the watchdog timer comprising a reset data detection circuit for detecting input reset data and outputting a reset signal, and a first counter that outputs a carry signal unless, before its count overflows, it receives a reset signal from said reset data detection circuit, wherein said reset data detection circuit comprises: a latch circuit for latching said reset data, a second counter for counting the number of times said reset signal is generated, and a comparator for comparing the output data from said latch circuit and said second counter and outputting said reset signal when the output data from said latch circuit and the output data from said second counter match, and the CPU is programmed to execute instructions for writing reset data into the latch circuit, the data written into the latch circuit correspondingly incrementing by 1 said second counter each time one of said instructions for writing the reset data is executed.

Claim 9

The combination according to claim 6, wherein the carry signal from the first counter is used to reset the CPU, whereupon the CPU resets and starts executing its program from address O.

Claim 10

A watchdog timer according to claim 6, wherein the latch circuit is connected to receive data from a data bus and latches the data upon receipt of a timer write signal which the CPU produces when it executes one of the instructions for writing the reset data in the latch circuit.

Claim 11

A watchdog timer according to claim 6, wherein the first counter receives and counts clock pulses which are periodically produced.

Claim 12

A watchdog timer according to claim 6, wherein the first counter starts counting up from 0 when it is reset.

Claim 13

A watchdog timer according to claim 6, further comprising a differentiating circuit receiving the output of the comparator and producing a pulse in synchronsim with a clock, and wherein the output of the differentiating circuit is applied to said first counter to reset it and to said second counter to increment it.