Digital modulator/demodulator including non-linear analog-to-digital converter and circuitry compensating for the non-linearity of the converter

Claim 2

A digital demodulator for demodulating an analog transmission signal on a line and converting the analog transmission signal to a linear digital signal, comprising: an analog-to-digital converter having a non-linear conversion characteristic which produces an output digital signal having a first predetermined number of bits non-linearly relative to the input analog transmission signal; and compensation means having a non-linear conversion characteristic which converts the non-linear digital signal output from the analog-to-digital converter into said linear digital signal having a second predetermined number of bits which is larger than the first predetermined number of bits.

Claim 3

A digital demodulator for demodulating an analog transmission signal on a line and converting the analog transmission signal to a linear digital signal, comprising: an analog-to-digital converter having a non-linear conversion characteristic which produces an output digital signal having a first predetermined number of bits non-linearly relative to the input analog transmission signal; compensation means having a non-linear conversion characteristic which converts the non-linear digital signal output from the analog-to-digital converter into said linear digital signal having a second predetermined number of bits which is larger than the first predetermined number of bits; and a digital signal processor which includes: first sampling means for sampling the digital signal output from the compensation means at a predetermined sampling rate; automatic gain control means for level-matching the sampled data output from the first sampling means and separating the sampled data into an in-phase component and an orthogonal component; demodulating means for demodulating the in-phase and orthogonal components output from the automatic gain control means; second sampling means for sampling the in-phase and orthogonal components output from the demodulating means at a predetermined timing which conforms to the transmission rate; level equalizing means for level equalizing the in-phase and orthogonal components output from the level equalizing means; phase shifting means for adjusting the phase of the in-phase and orthogonal components output from the level equalizing means; and quantizing means for quantizing and combining the in-phase and orthogonal components output from the phase shifting means to produce said linear digital signal.

Claim 4

A digital demodulator for demodulating an analog transmission signal on a line and converting the analog transmission signal to a linear digital signal, comprising: an analog-to-digital converter having a non-linear conversion characteristic which produces an output digital signal having a first predetermined number of bits non-linearly relative to the input analog transmission signal; compensation means having a non-linear conversion characteristic which converts the non-linear digital signal output from the analog-to-digital converter into said linear digital signal having a second predetermined number of bits which is larger than the first predetermined number of bits; and a digital signal processor which includes: first sampling means for sampling the digital signal output from the compensation means at a predetermined sampling rate; automatic gain control means for level-matching the sampled data output from the first sampling means and separating the sampled data into an in-phase component and an orthogonal component; demodulating means for demodulating the in-phase and orthogonal components output from the automatic gain control means; second sampling means for sampling the in-phase and orthogonal components output from the demodulating means at a predetermined timing which conforms to the transmission rate; level equalizing means for level equalizing the in-phase and orthogonal components output from the level equalizing means; phase shifting means for adjusting the phase of the in-phase and orthogonal components output from the level equalizing means; and quantizing means for quantizing and combining the in-phase and orthogonal components output from the phase shifting means to produce said linear digital signal.

Claim 5

A digital demodulator as claimed in claim 2, further comprising low pass filter means connected between the demodulating means and the second sampling means.

Claim 6

A digital demodulator for demodulating an analog transmission signal on a line and converting the analog transmission signal to a linear digital signal, comprising: an analog-to-digital converter having a non-linear conversion characteristic which produces an 8-bit output digital signal non-linearly relative to the input analog transmission signal; compensation means having a non-linear conversion characteristic which converts the 8-bit non-linear digital signal output from the analog-to-digital converter into said linear digital signal having a predetermined number of bits which is larger 8 bits, the compensation means comprising a 16-bit central processing unit; and a digital signal processor for processing the linear digital signal output from the compensation means.

Claim 7

A digital demodulator for demodulating an analog transmission signal on a line and converting the analog transmission signal to a linear digital signal, comprising: an analog-to-digital converter having a non-linear conversion characteristic which produces an 8-bit output digital signal non-linearly relative to the input analog transmission signal; compensation means having a non-linear conversion characteristic which converts the 8-bit non-linear digital signal output from the analog-to-digital converter into said linear digital signal having a predetermined number of bits which is larger 8 bits, the compensation means comprising a 16-bit central processing unit; and a digital signal processor for processing the linear digital signal output from the compensation means.

Claim 8

A digital demodulator as claimed in claim 4, in which said predetermined number of bits is 16 bits.