Circuit module with separate signal and power connectors

Claim 2

Connector apparatus comprising in combination: a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at last one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and at least one of said first and second surfaces having disposed thereon an outer conductive circuit pattern layer, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit partner layers, a plurality of conductive pins extending outwardly from one of said first and second surfaces, said pins being connected to preselected ones of said circuit pattern layers, and at least one of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, at least one inner conductive circuit pattern layer, said inner conductive circuit pattern layer of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layer of said second member; said circuit pattern layers of said first and second members being substantially parallel to a common reference plane.

Claim 3

Connector apparatus comprising in combination: a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and at least one of said first and second surfaces having disposed thereon an outer conductive circuit pattern layer, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from one of said first and second surfaces, said pins being connected to preselected ones of said circuit pattern layers, and at least one of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, at least one inner conductive circuit pattern layer, said inner conductive circuit pattern layer of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layer of said second member, said connector means being elongated other pins extending outwardly from said fifth surface.

Claim 4

Connector apparatus comprising in combination: a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and at least one of said first and second surfaces having disposed thereon an outer conductive circuit pattern layer, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from one of said first and second surfaces, said pins being connected to preselected ones of said circuit pattern layers, and at least one of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, at least one inner conductive circuit pattern layer, said inner conductive circuit pattern layer of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layer of said second member, said connector means being elongated other pins extending outwardly from said fifth surface.

Claim 5

Apparatus according to claim 2 wherein said ceramic first and second members are made of substantially the same material.

Claim 6

Apparatus according to claim 2 wherein each of said ends of said conductors of at least one of said first and second members are terminated with a cut conductive via.

Claim 7

Apparatus according to claim 4 wherein each of said cut conductive vias has an outer cut surface having a solder coating thereon.

Claim 8

Connector apparatus comprising in combination: a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and at least one of said first and second surfaces having disposed thereon an outer conductive circuit pattern layer, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from one of said first and second surfaces, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a multilayer ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layers of said second member; said circuit pattern layers of said first and second members being substantially parallel to a common reference plane.

Claim 9

Connector apparatus comprising in combination: a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and at least one of said first and second surfaces having disposed thereon an outer conductive circuit pattern layer, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from one of said first and second surfaces, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a multilayer ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layers of said second member; said circuit pattern layers of said first and second members being substantially parallel to a common reference plane.

Claim 10

Connector apparatus comprising in combination: a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and at least one of said first and second surfaces having disposed thereon an outer conductive circuit pattern layer, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from one of said first and second surfaces, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a multilayer ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layers of said second member, said connector means being elongated other pins extending outwardly from said fifth surface.

Claim 11

Connector apparatus comprising in combination: a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and at least one of said first and second surfaces having disposed thereon an outer conductive circuit pattern layer, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from one of said first and second surfaces, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a multilayer ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layers of said second member, said connector means being elongated other pins extending outwardly from said fifth surface.

Claim 12

Apparatus according to claim 7 wherein said ceramic first and second members are made of substantially the same material.

Claim 13

Apparatus according to claim 7 wherein each of said ends of said conductors of at least one of said first and second members are terminated with a cut conductive via.

Claim 14

Apparatus according to claim 9 wherein each of said cut conductive vias has an outer cut surface having a solder coating thereon.

Claim 15

Integrated circuit package apparatus comprising in combination: at least one integrated circuit chip having plural input/output terminals; a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chip being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and at least one of said inner conductive circuit pattern layers having plural conductor extended to said third surface and having ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, at least one inner conductive circuit pattern layer, said inner conductive circuit pattern layer of said second member having plurality conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layer of said second member; preselected ones of said input/output terminals of said chip being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chip being interconnected by said interconnected circuit pattern layers of said first member to said pins, said circuit pattern layers of said first and second members being substantially parallel to a common reference plane.

Claim 16

Integrated circuit package apparatus comprising in combination: at least one integrated circuit chip having plural input/output terminals; a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chip being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and at least one of said inner conductive circuit pattern layers having plural conductor extended to said third surface and having ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, at least one inner conductive circuit pattern layer, said inner conductive circuit pattern layer of said second member having plurality conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layer of said second member; preselected ones of said input/output terminals of said chip being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chip being interconnected by said interconnected circuit pattern layers of said first member to said pins, said circuit pattern layers of said first and second members being substantially parallel to a common reference plane.

Claim 17

Integrated circuit package apparatus comprising in combination: at least one integrated circuit chip having plural input/output terminals; a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chip being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and at least one of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, at least one inner conductive circuit pattern layer, said inner conductive circuit pattern layer of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layer of said second member; preselected ones of said input/output terminals of said chip being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chip being interconnected by said interconnected circuit pattern layers of said first member to said pins, said connector means being elongated other pins extending outwardly from said fifth surface.

Claim 18

Integrated circuit package apparatus comprising in combination: at least one integrated circuit chip having plural input/output terminals; a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, and said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chip being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and at least one of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, at least one inner conductive circuit pattern layer, said inner conductive circuit pattern layer of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layer of said second member; preselected ones of said input/output terminals of said chip being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chip being interconnected by said interconnected circuit pattern layers of said first member to said pins, said connector means being elongated other pins extending outwardly from said fifth surface.

Claim 19

Apparatus according to claim 12 wherein said ceramic first and second members are made of substantially the same material.

Claim 20

Apparatus according to claim 12 wherein each of said ends of said conductors of at least one of said first and second members are terminated with a cut conductive via.

Claim 21

Apparatus according to claim 14 wherein each of said cut conductive vias has an outer cut surface having a solder coating thereon.

Claim 22

Apparatus according to claim 12 wherein said apparatus further comprises: a printed circuit board, said printed circuit board having first socket means; and at least one electrical connector having second socket means; said pins extending from said second surface of said first member being plugged into said first socket means of said printed circuit board, and said other pins extending from said fifth surface of said second member being plugged into said second socket means of said at least one electrical connector.

Claim 23

Apparatus according to claim 16 wherein input/output data signals for/from said chip are passed through said first socket means, and power signals for said chip are passed through said second socket means.

Claim 24

Integrated circuit package apparatus comprising in combination: a plurality of integrated circuit chips, each of said chips having plural input/output terminals; a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chips being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layers of said second member; preselected ones of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers of said first member to said pins, said circuit pattern layers of said first and second members being substantially parallel to a common reference plane.

Claim 25

Integrated circuit package apparatus comprising in combination: a plurality of integrated circuit chips, each of said chips having plural input/output terminals; a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chips being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layers of said second member; preselected ones of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers of said first member to said pins, said circuit pattern layers of said first and second members being substantially parallel to a common reference plane.

Claim 26

Integrated circuit package apparatus comprising in combination: a plurality of integrated circuit chips, each of said chips having plural input/output terminals; a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chips being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layers of said second member; preselected ones of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers of said first member to said pins, said connector means being elongated other pins extending outwardly from said fifth surface.

Claim 27

Integrated circuit package apparatus comprising in combination: a plurality of integrated circuit chips, each of said chips having plural input/output terminals; a planar multilayer ceramic substrate first member having planar outer first and second opposite surfaces and at least one outer edge third surface therebetween, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chips being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to said third surface and having the ends thereof exposed outwardly thereat; and a ceramic second member having opposite outer fourth and fifth surfaces, said first and second members having their respective said third and fourth surfaces juxtaposed adjacent to each other, a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to said fourth surface and having the ends thereof exposed outwardly thereat, said ends of said plural conductors of said first member being mated with said ends of said plural conductors of said second member, and a plurality of connector means disposed at said fifth surface and connected to said circuit pattern layers of said second member; preselected ones of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers of said first member to said pins, said connector means being elongated other pins extending outwardly from said fifth surface.

Claim 28

Apparatus according to claim 19 wherein said ceramic first and second members are made of substantially the same material.

Claim 29

Apparatus according to claim 19 wherein each of said ends of said conductors of at least one of said first and second members are terminated with a cut conductive via.

Claim 30

Apparatus according to claim 21 wherein each of said cut conductive vias has an outer cut surface having a solder coating thereon.

Claim 31

Apparatus according to claim 19 wherein said apparatus further comprises: a printed circuit board, said printed circuit board having first socket means; and at least one electrical connector having second socket means; said pins extending from said second surface of said first member being plugged into said first socket means of said printed circuit board, and said other pins extending from said fifth surface of said second member being plugged into said second socket means of said at least one electrical connector.

Claim 32

Apparatus according to claim 23 wherein input/output data signals for/from said chips are passed through said first socket means, and power signals for said chips are passed through said second socket means.

Claim 33

Integrated circuit package apparatus comprising in combination: a plurality of integrated circuit chips, each of said chips having plural input/output terminals, a planar multilayer ceramic rectangular substrate first member having planar outer first and second opposite parallel surfaces and four outer edge third surfaces between and orthogonal to said first and second surfaces, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chips being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to three of said third surfaces and having the ends thereof exposed outwardly thereat; and a ceramic second member having a compatible rectangular opening therethrough for receiving therein said first member, said rectangular opening having four wall fourth surfaces, said second member having four outer fifth surfaces, each of said fourth surfaces being opposite a mutually exclusive one of said fifth surfaces, said first member when received in said opening having the respective third surfaces thereof juxtaposed to a mutually exclusive one of said fourth surfaces, said second member further having a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to three of said fourth surfaces and having the ends thereof exposed outwardly thereat, said three fourth surfaces being juxtaposed to said three third surfaces when said first member is received in said opening, each of said ends at said three third surfaces of said first member being mated with a mutually exclusive one of said ends at said three fourth surfaces, and a plurality of connector means disposed at at least one of said fifth surfaces and connected to said circuit pattern layers of said second member, preselected ones of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers of said first member to said pins.

Claim 34

Integrated circuit package apparatus comprising in combination: a plurality of integrated circuit chips, each of said chips having plural input/output terminals, a planar multilayer ceramic rectangular substrate first member having planar outer first and second opposite parallel surfaces and four outer edge third surfaces between and orthogonal to said first and second surfaces, a plurality of planar inner conductive circuit pattern layers disposed between said first and second surfaces, said first surface having disposed thereon an outer conductive circuit pattern layer, said integrated circuit chips being mounted to said first surface and having said input/output terminals connected to said outer conductive circuit pattern layer thereof, a plurality of conductive vias within said substrate member for selectively interconnecting said conductive circuit pattern layers, a plurality of conductive pins extending outwardly from said second surface, said pins being connected to preselected ones of said circuit pattern layers, and a predetermined plural number of said inner conductive circuit pattern layers having plural conductors extended to three of said third surfaces and having the ends thereof exposed outwardly thereat; and a ceramic second member having a compatible rectangular opening therethrough for receiving therein said first member, said rectangular opening having four wall fourth surfaces, said second member having four outer fifth surfaces, each of said fourth surfaces being opposite a mutually exclusive one of said fifth surfaces, said first member when received in said opening having the respective third surfaces thereof juxtaposed to a mutually exclusive one of said fourth surfaces, said second member further having a plural corresponding said number of inner conductive circuit pattern layers, said inner conductive circuit pattern layers of said second member having plural conductors extended to three of said fourth surfaces and having the ends thereof exposed outwardly thereat, said three fourth surfaces being juxtaposed to said three third surfaces when said first member is received in said opening, each of said ends at said three third surfaces of said first member being mated with a mutually exclusive one of said ends at said three fourth surfaces, and a plurality of connector means disposed at at least one of said fifth surfaces and connected to said circuit pattern layers of said second member, preselected ones of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers to said connector means, and the other of said input/output terminals of said chips being interconnected by said interconnected circuit pattern layers of said first member to said pins.

Claim 35

Apparatus according to claim 25 wherein said ceramic first and second members are made of substantially the same material.

Claim 36

Apparatus according to claim 25 wherein each of said ends of said conductors of said first and second members are terminated with a cut conductive via.

Claim 37

Apparatus according to claim 27 wherein each of said cut conductive vias has an outer cut surface having a solder coating thereon.

Claim 38

Apparatus according to claim 25 wherein said connector means are elongated other pins extending outwardly from said fifth surface.

Claim 39

Apparatus according to claim 29 wherein said apparatus further comprises: a printed circuit board, said printed circuit board having first socket means; and at least one electrical connector having second socket means; said pins extending from said second surface of said first member being plugged into said first socket means of said printed circuit board, and said other pins extending from said fifth surface of said second member being plugged into said second socket means of said at least one electrical connector.

Claim 40

Apparatus according to claim 30 wherein input/output data signals for/from said chips are passed through said first socket means, and power signals for said chips are passed through said second socket means.