Patent US4820653A successfully refreshed from Google Patents.
US4820653A
Expired / Lapsed
US
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Technique for fabricating complementary dielectrically isolated wafer
Assignee: AT&T Inc
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Filing: 1988-02-12
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Granted: 1989-04-11
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Expires: 2008-02-12
Abstract
Abstract A method has been developed for providing tub regions with various resistivities in a dielectrically isolated (DI) structure. The starting substrate material is etched to expose the locations designated for a resistivity modification, and epitaxial material of the modified resistivity value is used to fill the exposed tubs. The remainder of the fabrication process follows conventional DI fabrication techniques. The procedure may simply be used to create a DI structure containing both n-type and p-type tube regions. The idea may also be extended, however, to providing separate tubs with, for example, n+ resistivity, n- resistivity, p- resistivity and p+ resistivity, all within the same DI structure.
Inventors
- 👤 William G. Easter
- 👤 Daniel D. Leffel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:46
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
103 words
In the fabrication of a dielectrically isolated device, a method of forming regions of at least two different resistivities, in the initial silicon substrate, the method comprising the steps of: (a) providing a single crystal silicon substrate of a first conductivity type; (b) patterning said substrate to define locations selected to comprise a first resistivity value; (c) etching said substrate to remove material from the locations defined in step (b); (d) forming epitaxial material of the first resistivity value in the locations exposed in step (c); (e) repeating steps (b)-(d) for subsequent group locations, each group defined to comprise a different resistivity value.
Claim 2
Dependent Claim
103 words
In the fabrication of a dielectrically isolated device, a method of forming regions of at least two different resistivities, in the initial silicon substrate, the method comprising the steps of: (a) providing a single crystal silicon substrate of a first conductivity type; (b) patterning said substrate to define locations selected to comprise a first resistivity value; (c) etching said substrate to remove material from the locations defined in step (b); (d) forming epitaxial material of the first resistivity value in the locations exposed in step (c); (e) repeating steps (b)-(d) for subsequent group locations, each group defined to comprise a different resistivity value.
Claim 3
Dependent Claim
18 words
The method of claim 1 wherein the substrate is p-type and n-type polysilicon is formed in step (d).
Claim 4
Dependent Claim
22 words
The method of claim 1 where in performing step (d), a chemical vapor deposition technique is used to form the epitaxial material.
Claim 5
Dependent Claim
22 words
The method of claim 1 where in performing step (d), a selective epitaxial growth process is used to form the epitaxial material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-10 | 1992-10-10 | 1993-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-10 | 1996-10-10 | 1997-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-10 | 2000-10-10 | 2001-04-11 | $7700.00 | Window Closed / Lapsed |