Patent US4831433A successfully refreshed from Google Patents.
US4831433A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Toshiba Corp
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Filing: 1988-07-27
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Granted: 1989-05-16
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Expires: 2008-07-27
Abstract
Abstract A semiconductor device includes a rectangular semiconductor chip, first to fourth memory cell arrays formed on the semiconductor chip, and first to fourth bonding pads formed on the peripheral part of the semiconductor chip. In this semiconductor device in particular, first bonding pads are disposed along a first long side of the semiconductor chip while second bonding pads are disposed along a second long side of the chip. The first and second memory cell arrays are disposed between the first bonding pads and the second long side while the third and fourth memory cell arrays are disposed between the first long side and the second pads.
Inventors
- 👤 Mitsugi Oguara
- 👤 Fumio Horiguchi
- 👤 Shigeyoshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:05
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10B; H10B12/00; H10D; H10D89/00; H10D89/10; H10W72/50; H10W72/541; H10W72/5449; H10W72/931; H10W72/932; H10W90/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
170 words
A semiconductor memory device comprising: a rectangular semiconductor chip having a top surface and longitudinal and lateral sides; at least first, second, third, and fourth memory arrays positioned on said top surface in a staggered, eccentric configuration on said semiconductor chip relative to said longitudinal sides of said semiconductor chip such that a first edge of said first and third memory arrays are spaced a first predetermined distance from respective opposing longitudinal sides of said chip, and a first edge of said second and fourth memory arrays are spaced a second predetermined distance, less than said first predetermined distance, from each of said opposing longitudinal sides of said chip to form a narrow space and a wide space between said first edges of respective memory arrays and each said longitudinal side of said chip; and a plurality of bonding pads positioned on said top surface of said chip in said wide space between said first edges of respective ones of said memory arrays and respective longitudinal sides of said chip.
Claim 2
Dependent Claim
170 words
A semiconductor memory device comprising: a rectangular semiconductor chip having a top surface and longitudinal and lateral sides; at least first, second, third, and fourth memory arrays positioned on said top surface in a staggered, eccentric configuration on said semiconductor chip relative to said longitudinal sides of said semiconductor chip such that a first edge of said first and third memory arrays are spaced a first predetermined distance from respective opposing longitudinal sides of said chip, and a first edge of said second and fourth memory arrays are spaced a second predetermined distance, less than said first predetermined distance, from each of said opposing longitudinal sides of said chip to form a narrow space and a wide space between said first edges of respective memory arrays and each said longitudinal side of said chip; and a plurality of bonding pads positioned on said top surface of said chip in said wide space between said first edges of respective ones of said memory arrays and respective longitudinal sides of said chip.
Claim 3
Dependent Claim
38 words
A semiconductor memory device according to claim 1, wherein each memory array is substantially rectangular with longitudinal and lateral sides and said lateral sides of said memory arrays are positioned opposite the longitudinal sides of said semiconductor chips.
Claim 4
Dependent Claim
27 words
A semiconductor memory device according to claim 1, wherein said memory arrays are spaced from said lateral sides of said semiconductor chip to form bonding spaces therebetween.
Claim 5
Dependent Claim
161 words
A semiconductor device comprising: a rectangular semiconductor chip having a top surface and longitudinal and lateral sides; at least first, second, third, and fourth element regions positioned on said top surface in a staggered, eccentric configuration relative to said longitudinal sides of said semiconductor chip such that a first edge of said first and third element regions are spaced a first predetermined distance from opposite longitudinal sides of said chip, and a first edge of said second and fourth element regions are spaced a second predetermined distance, less than said first predetermined distance, from opposite longitudinal sides of said chip to form a narrow space and a wide space between said first edges of respective ones of said element regions and each said longitudinal side of said chip; and a plurality of bonding pads positioned on said top surface of said chip in said wide region between respective first edges of said element regions and respective longitudinal sides of said chip.
Claim 6
Dependent Claim
161 words
A semiconductor device comprising: a rectangular semiconductor chip having a top surface and longitudinal and lateral sides; at least first, second, third, and fourth element regions positioned on said top surface in a staggered, eccentric configuration relative to said longitudinal sides of said semiconductor chip such that a first edge of said first and third element regions are spaced a first predetermined distance from opposite longitudinal sides of said chip, and a first edge of said second and fourth element regions are spaced a second predetermined distance, less than said first predetermined distance, from opposite longitudinal sides of said chip to form a narrow space and a wide space between said first edges of respective ones of said element regions and each said longitudinal side of said chip; and a plurality of bonding pads positioned on said top surface of said chip in said wide region between respective first edges of said element regions and respective longitudinal sides of said chip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |