Patent US4833596A successfully refreshed from Google Patents.
US4833596A
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Logical arrangement for controlling use of different system displays by main processor and co-processor
Assignee: International Business Machines Corp
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Filing: 1988-03-23
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Granted: 1989-05-23
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Expires: 2008-03-23
Abstract
Abstract A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. In a second mode, a display is time-shared between processors by establishing a virtual video buffer in main memory which is written into by one processor when the other processor has control of the display device. The contents of the virtual and real buffer are swapped whenever the display is reassigned to the other processor. In the third mode, co-processor data in the virtual buffer can be "windowed" onto the display device when it is assigned to the main processor. In the fourth mode, a display assigned to the co-processor displays data being run by code that is written to the displayed on a display device with a different pel resolution. The main processor does a pel conversion operation on the data in the process of transferring the data from the virtual buffer to the real buffer.
Inventors
- 👤 Patrick A. Buckland
- 👤 John W. Irwin
- 👤 Jack E. Reeder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:58
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F3/153; G09; G09G; G09G5/00; G09G5/22; G09G5/222; G09G2360/00; G09G2360/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
226 words
In a data processing system having a main processor, a memory subsystem, and an Input/Output subsystem including an Input/Output Channel Controller an I/O bus, and a plurality of units connected to said bus including a co-processor and a plurality of display devices, each having a different reserved I/O address space and each including a real video buffer and control registers for storing display control signals from one of said processors for controlling the display of data that is entered into said real buffer, the improvement comprising in combination display control means associated with said co-processor and setable by said main processor to control whether said co-processor, in executing a move instruction involving a transfer of a byte of data from main memory to one of said real video buffers, transfers said byte of data, suppresses the transfer of said byte of data, or transfers said byte of data to a corresponding virtual video buffer in said main memory, said display control means including mode register means setable by said main processor and address trap logic circuits for indicating when an instruction being executed by said co-processor involves an address that is within the range of I/O address space that is reserved for said display devices to permit said display control means to operate said system in accordance with the mode data supplied by said main processor.
Claim 2
Dependent Claim
226 words
In a data processing system having a main processor, a memory subsystem, and an Input/Output subsystem including an Input/Output Channel Controller an I/O bus, and a plurality of units connected to said bus including a co-processor and a plurality of display devices, each having a different reserved I/O address space and each including a real video buffer and control registers for storing display control signals from one of said processors for controlling the display of data that is entered into said real buffer, the improvement comprising in combination display control means associated with said co-processor and setable by said main processor to control whether said co-processor, in executing a move instruction involving a transfer of a byte of data from main memory to one of said real video buffers, transfers said byte of data, suppresses the transfer of said byte of data, or transfers said byte of data to a corresponding virtual video buffer in said main memory, said display control means including mode register means setable by said main processor and address trap logic circuits for indicating when an instruction being executed by said co-processor involves an address that is within the range of I/O address space that is reserved for said display devices to permit said display control means to operate said system in accordance with the mode data supplied by said main processor.
Claim 3
Dependent Claim
45 words
The system set forth in claim 1 in which said said display control means includes a relocate address register which is setable by said main processor with a high order partial address that defines an area of main memory for locating said corresponding virtual buffer.
Claim 4
Dependent Claim
50 words
The system set forth in claim 2, further including circuit means for disabling the memory read-write control lines from said co-processor in response to mode control data to suppress transfer of a byte of data to an address range reserved for a display device assigned exclusively to said main processor.
Claim 5
Dependent Claim
55 words
The system set forth in claim 3, further including means associated with said co-processor for sending an interrupt request signal to said main processor in response to a relocate write operation to said virtual buffer, to permit subsequent action by said main processor relative to the data that has been relocated to said virtual buffer.
Claim 6
Dependent Claim
43 words
The system set forth in claim 4, further including interrupt servicing means associated with said main processor for transferring data from said virtual buffer to said real buffer in accordance with the mode control data and in response to said interrupt request signal.
Claim 7
Dependent Claim
89 words
The system set forth in claim 5 in which said display control means includes circuit means for establishing a circular queue in said area of main memory which contains said virtual buffer to list buffer address locations that have been involved in the relocate write operations to said virtual buffer, said circuit means including a counter, a queue size register, a queue limit register, and a comparator for comparing the contents of said counter and said queue limit register to provide an indication of the status of said queue.
Claim 8
Dependent Claim
45 words
The system set forth in claim 6, including means to load said queue limit register with data from said main processor in response to reading a buffer address location from said list and transferring data in said virtual buffer address location to said real buffer.
Claim 9
Dependent Claim
33 words
The system set forth in claim 7 in which said main processor includes means for "windowing" data in said virtual buffer into a display on a display device assigned to said main processor.
Claim 10
Dependent Claim
52 words
The system set forth in claim 7 in which said main processor includes means for converting data stored in a virtual buffer assigned to said co-processor by a program which supports a display device of one pel resolution to permit displaying said data on a display device having a different pel resolution.
Claim 11
Dependent Claim
39 words
The system set forth in claim 2 in which the contents of said virtual buffer and said real buffer are interchangeable under control of said main processor and in accordance with the mode control data supplied to said processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-22 | 1992-11-21 | 1993-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-22 | 1996-11-21 | 1997-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-22 | 2000-11-21 | 2001-05-23 | $7700.00 | Window Closed / Lapsed |