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Patent US4833657A successfully refreshed from Google Patents.
US4833657A
Expired / Lapsed
US
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Semiconductor frame buffer memory
Assignee: Toshiba Corp
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Filing: 1986-10-24
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Granted: 1989-05-23
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Expires: 2006-10-24
Abstract
Abstract A semiconductor memory for writing or reading data words in response to prescribed bank address data and bit address data, each word having a prescribed amount of bits, is described. The memory includes a memory array for storing the data words. The memory array includes at least two memory banks adjacent to one another, each bank having a bit area corresponding to the prescribed amount of bits, buffer memory for temporarily storing the data word for writing into the memory array or the data word read from the memory array, a first source for applying the bank address data to the memory array to access the memory banks, a second source for applying the bit address data to the memory banks to access prescribed bit locations of the memory banks, and logic circuitry responsive to the bit address data for cyclically shifting the data word stored in the buffer memory by an amount corresponding to the value of the received bit address data.
Inventors
- 👤 Shigeru Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:51
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G06; G06F; G06F12/00; G06F12/02; G06F12/04; G06T; G06T1/00; G06T1/60
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
174 words
A semiconductor memory for writing or reading data words in response to prescribed bank address data and bit address data, each word having a prescribed amount of bits, the memory comprising: memory array means for storing the data words, the memory array means including at least two memory banks adjacent to one another, each band having a bit area corresponding to the prescribed amount of bits; buffer memory means for a temporarily storing at least one of the data word for writing into the memory array means and the data word read from the memory array means; first source means for applying the bank address data to the memory array means to access to the memory banks; second source means for applying the bit address data to the memory banks to access prescribed bit locations of the memory banks; and logic circuit means responsive to the bit address data for cyclically shifting the data word stored in the buffer memory means by an amount corresponding to the value of the received bit address data.
Claim 2
Dependent Claim
174 words
A semiconductor memory for writing or reading data words in response to prescribed bank address data and bit address data, each word having a prescribed amount of bits, the memory comprising: memory array means for storing the data words, the memory array means including at least two memory banks adjacent to one another, each band having a bit area corresponding to the prescribed amount of bits; buffer memory means for a temporarily storing at least one of the data word for writing into the memory array means and the data word read from the memory array means; first source means for applying the bank address data to the memory array means to access to the memory banks; second source means for applying the bit address data to the memory banks to access prescribed bit locations of the memory banks; and logic circuit means responsive to the bit address data for cyclically shifting the data word stored in the buffer memory means by an amount corresponding to the value of the received bit address data.
Claim 3
Dependent Claim
45 words
The memory of claim 1, wherein the logic circuit means includes an output control circuit responsive to a read/write signal for changing the buffer memory means between the read operation mode and the write operation mode and for determining the direction of the cyclic shifting.
Claim 4
Dependent Claim
49 words
The memory of claim 2, wherein the logic circuit means includes a shift control circuit for respectively effecting control to establish high impedance states and normal output states in response to the LSB of the bank address data as well as to the values of said bit address data.
Claim 5
Dependent Claim
62 words
The memory of claim 3, wherein the logic circuit means includes a control circuit for said output control circuit for a read-out control to respectively effect control to establish high impedance states and to determine bit positions at which read-out is effected in response to the LSB of the bank address data as well as to the values of said bit addresses.
Claim 6
Dependent Claim
61 words
The memory of claim 3, wherein the logic circuit means includes a control circuit for said output control circuit for a write-in control to respectively effect control to establish write-in states and to determine bit positions at which write-in is effected in response to the LSB of the bank address data as well as to the values of said bit addresses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-22 | 1992-11-21 | 1993-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-22 | 1996-11-21 | 1997-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-22 | 2000-11-21 | 2001-05-23 | $7700.00 | Window Closed / Lapsed |