Look-up table

Claim 2

A look-up table for interfacing between a plurality of address lines output from a memory frame buffer and a plurality of data lines input to a color monitor in a digital, color graphics display apparatus, said table comprising: means for duplicating some of said address lines of said memory frame buffer; first addressable memory means for receiving said address lines and said duplicated address lines and for generating a first output signal from the location addressed, wherein the number of data lines containing said first output signal is less than the address and duplicated address lines to said first memory means; second addressable memory means for receiving said first output signal as an address therefor and for generating a second output signal from the location addressed, wherein the number of data lines containing said second output signal is less than the address lines to said second memory means; and third addressable memory means for receiving said second output signal as an address therefor and for generating a third output signal from the location addressed and for supplying said third output signal to said color monitor, and wherein the number of data lines containing said third output signal is less than the address lines to said third memory means.

Claim 3

The look-up table of claim 1 wherein said duplicating means duplicates all of said output of said memory frame buffer.

Claim 4

The look-up table of claim 1 wherein said first memory means comprises a plurality of second memories.

Claim 5

The look-up table of claim 3 wherein said second memory means comprises a plurality of second memories.

Claim 6

The look-up table of claim 4 wherein said third memory means comprises a plurality of third memories.

Claim 7

A look-up table for receiving a plurality of groups of input address lines, and for generating a plurality of output data lines therefrom, said look-up table comprising: means for duplicating some of the groups of input address lines; a first memory bank means including a plurality of directly addressable first memories, each first memory having a plurality of first input address lines and a plurality of first output data lines wherein the number of first output data lines is less than said first input address lines; first connecting means for interconnecting said plurality of groups of input address lines and said duplicated groups of input address lines to the first input address of said first memories; a second memory bank means including a plurality of directly addressable second memories, each second memory having a plurality of second input address lines and a plurality of second output data lines wherein the number of second output data lines is less than said second input address lines; second connecting means for interconnecting the first output data lines to the second input address lines; a third memory bank means including a plurality of directly addressable third memories, each third memory having a plurality of third input address lines and a plurality of third output data lines is less than said third input address lines; and third connecting means for interconnecting the second output data lines to the third input address lines; whereby said third output data lines is said output of said look-up table.

Claim 8

A look-up table for receiving a plurality of groups of input address lines, and for generating a plurality of output data lines therefrom, said look-up table comprising: means for duplicating some of the groups of input address lines; a first memory bank means including a plurality of directly addressable first memories, each first memory having a plurality of first input address lines and a plurality of first output data lines wherein the number of first output data lines is less than said first input address lines; first connecting means for interconnecting said plurality of groups of input address lines and said duplicated groups of input address lines to the first input address of said first memories; a second memory bank means including a plurality of directly addressable second memories, each second memory having a plurality of second input address lines and a plurality of second output data lines wherein the number of second output data lines is less than said second input address lines; second connecting means for interconnecting the first output data lines to the second input address lines; a third memory bank means including a plurality of directly addressable third memories, each third memory having a plurality of third input address lines and a plurality of third output data lines is less than said third input address lines; and third connecting means for interconnecting the second output data lines to the third input address lines; whereby said third output data lines is said output of said look-up table.

Claim 9

The look-up table of claim 6 wherein said duplicating means duplicates all of the groups of input lines.

Claim 10

The look-up table of claim 7 wherein said first connecting means comprises: means for interconnecting one of said group of input lines and another group of duplicated input lines to the first input address of each first memories.

Claim 11

The look-up table of claim 6 wherein said second connecting means comprises: means for interconnecting one of the first output lines of each first memory to one of the second input address of each second memory.

Claim 12

The look-up table of claim 6 wherein said third connecting means comprises: means for interconnecting one of the second output lines of each second memory to one of the second input address of each third memory.