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US4847751A
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Multi-task execution control system
Assignee: Sharp Corp
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Filing: 1987-06-08
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Granted: 1989-07-11
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Expires: 2007-06-08
Abstract
Abstract In a microcomputer system, having independently programmed tasks and a master control processing unit (CPU), tasks can be switched independent of the master CPU through the use of a multi-task support processor which may, for example, be connected to the microcomputer system via an input/output (I/O) port. The multi-task support processor includes a memory for storing task control programs, a data memory and task control memory, a timer, a controller for controlling multi-task operations, and a master CPU interface element. Tasks including task control commands are stored in a memory for execution by the master CPU. The master CPU, upon encountering a task control command, sends that command to the multi-task support processor which becomes activated to control the switching and communications between the tasks under the direction of the received task control command, so that tasking control may be performed independent of the master CPU.
Inventors
- 👤 Toshimitsu Nakade
- 👤 Masaru Kuki
- 👤 Takaaki Uno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:04
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F9/4881
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
155 words
A multi-task execution control system for a microcomputer having only a single central processor unit comprising: memory means for storing a plurality of independently programmed tasks, said plurality of independently programmed tasks including a plurality of task control commands; said single central processor unit (CPU) executing said plurality of tasks; and multi-task support processor means, external from and operatively connected to said central processor means and responsive to said task control commands, for controlling the switching and communication of said plurality of tasks for execution by said central processing unit; said central processor unit, upon execution of an activation task control command included in an independently programmed task, sending said activation task control command to said multi-task support processor means; said multi-task support processor means controlling the switching of and the communication between said plurality of tasks under the direction of said activation task control command independently of the architecture of said central processor unit.
Claim 2
Dependent Claim
155 words
A multi-task execution control system for a microcomputer having only a single central processor unit comprising: memory means for storing a plurality of independently programmed tasks, said plurality of independently programmed tasks including a plurality of task control commands; said single central processor unit (CPU) executing said plurality of tasks; and multi-task support processor means, external from and operatively connected to said central processor means and responsive to said task control commands, for controlling the switching and communication of said plurality of tasks for execution by said central processing unit; said central processor unit, upon execution of an activation task control command included in an independently programmed task, sending said activation task control command to said multi-task support processor means; said multi-task support processor means controlling the switching of and the communication between said plurality of tasks under the direction of said activation task control command independently of the architecture of said central processor unit.
Claim 3
Dependent Claim
101 words
A system, as recited in claim 1, wherein said multi-task support processor means includes, first memory means for storing control programs for controlling the switching and communication between said plurality of tasks, interface-means, operatively connected to said central processor unit for sending data to and receiving data from said central processor means, second memory means, connected to said interface means for storing system configuration data received from said central processing unit, and control means, responsive to said control programs and said task control command received from said central processor unit, for controlling the switching and communication between said plurality of tasks.
Claim 4
Dependent Claim
39 words
A system, as recited in claim 2, wherein said second memory means stores priority data corresponding to said plurality of tasks, and said control means controls the switching between said plurality of tasks in accordance with said priority data.
Claim 5
Dependent Claim
45 words
A system, as recited in claim 2, further comprising, input/output means, external from and operatively connected to said central processor means, for inputting data to said central processor unit from an external device and outputting data from said central processor means to said external device.
Claim 6
Dependent Claim
36 words
A system, as recited in claim 2, wherein said control means initiates switching between said plurality of tasks by causing said interface means to receive or transmit said plurality of tasks to said central processor unit.
References Cited (Backward Citations)
US3158317A
Cited
US3187321A
Cited
US3533076A
Cited
US4152761A
Cited
US4384324A
Cited
US4493020A
Cited
US4543630A
Cited
US4553202A
Cited
US4591976A
Cited
US4604694A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-10 | 1993-01-09 | 1993-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-10 | 1997-01-09 | 1997-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-10 | 2001-01-09 | 2001-07-11 | $7700.00 | Window Closed / Lapsed |