Patent US4847800A successfully refreshed from Google Patents.
US4847800A
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Input register for test operand generation
Assignee: Control Data Corp
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Filing: 1987-10-23
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Granted: 1989-07-11
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Expires: 2007-10-23
Abstract
Abstract Sequential faults are not tested for adequately when using test input operands generated in the chip from a random number generator to test the logic circuits in a very large scale integrated (VLSI) chip. Accordingly this application teaches the efficient construction of a test operand generator, using an input register with properly randomized feedback to break up sequential patterns which would otherwise develop in the input register.
Inventors
- 👤 Don A. Daane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318385; G01R31/31813; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
187 words
In a VLSI circuit, an input register useful at least for generating sequentially pseudorandom input operands, wherein the input register is a serial shift register comprised of a chain of serially shifted flip-flops from first to last having a serially shifted external input to the first flip-flop of said input register, comprising, when configured to generate such operands; a plurality of connected segments of unequal length wherein the output of the last flip-flop in each segment is fed back into predetermined flip-flops within that segment, such predetermined flip-flops being of a number less than the number of flip-flops in that segment, and wherein the feedback is XORed into each such predetermined flip-flop with the output of the flip-flop that precedes the particular predetermined flip-flop in the chain and wherein the first flip-flop of the first segment receives the XORed with the external input, and wherein the other of the first flip-flops of the other segments in said plurality receive input from the last flip-flops of the just preceding segment XORed with the output from the last flip-flop of said other segment in which said first flip-flop exists.
Claim 2
Dependent Claim
187 words
In a VLSI circuit, an input register useful at least for generating sequentially pseudorandom input operands, wherein the input register is a serial shift register comprised of a chain of serially shifted flip-flops from first to last having a serially shifted external input to the first flip-flop of said input register, comprising, when configured to generate such operands; a plurality of connected segments of unequal length wherein the output of the last flip-flop in each segment is fed back into predetermined flip-flops within that segment, such predetermined flip-flops being of a number less than the number of flip-flops in that segment, and wherein the feedback is XORed into each such predetermined flip-flop with the output of the flip-flop that precedes the particular predetermined flip-flop in the chain and wherein the first flip-flop of the first segment receives the XORed with the external input, and wherein the other of the first flip-flops of the other segments in said plurality receive input from the last flip-flops of the just preceding segment XORed with the output from the last flip-flop of said other segment in which said first flip-flop exists.
Claim 3
Dependent Claim
55 words
An input register as set forth in claim 1, wherein the number of said predetermined flip-flops is an even integer with a value close to either one-third or two-thirds of the number of flip-flops in the segment, and wherein said last flip-flop output is also fed back to the least significant bit of each segment.
Claim 4
Dependent Claim
37 words
An input register as set forth in claim 1, wherein the number of flip-flops in each segment is a different number, n, and wherein the value 2 n -1 is relatively prime for to each other segment.
Claim 5
Dependent Claim
15 words
An input register as set forth in claim 3, wherein the largest segment is first.
Claim 6
Dependent Claim
51 words
An input register as set forth in claim 4 wherein the particular flip-flop means to which feedback are provided are determined by a polynomial such that the maximum length non repeating sequence equal to 2 to the power of the number of flip-flops in the segment length, minus the number 1.
Claim 7
Dependent Claim
50 words
An input register as set forth in claim 3 wherein the particular flip-flop means to which feedback are provided are determined by a polynomial such that the maximum length non-repeating sequence equal to 2 to the power of the number of flip-flops in the segment length, minus the number 1.
Claim 8
Dependent Claim
21 words
An input register as set forth in claim 1, wherein the input register further comprises, when configured to produce input operands:
Claim 9
Dependent Claim
50 words
An input register as set forth in claim 7 wherein the particular flip-flop means to which feedback are provided are determined by a polynomial such that the maximum length non-repeating sequence equal to 2 to the power of the number of flip-flops in the segment length, minus the number 1.
Claim 10
Dependent Claim
15 words
An input register as set forth in claim 1, wherein the largest segment is first.
Claim 11
Dependent Claim
52 words
An input register as set forth in claim 1 wherein the particular flip-flop means to which feedback are provided are determined by a polynomial such that the maximum length non-repeating sequence equal to 2 to the power of the number of flip-flops in the segment length, minus the number 1, is achieved.
Claim 12
Dependent Claim
50 words
An input register as set forth in claim 1 wherein the particular flip-flop means to which feedback are provided are determined by a polynomial such that the maximum length non-repeating sequence equal to 2 to the power of the number of flip-flops in the segment length, minus the number 1.
Claim 13
Dependent Claim
194 words
An input register as set forth in claim 1, wherein the input register is comprised of four segments of bit lengths 67, 63, 64, and 55, in that order connected serially, and wherein the the most significant bit output of each segment is fed back to certain bits of the register, the last bit of the first segment fed back to bits 0, 3, 5, 8, 12, 13, 15, 20, 24, 26, 27, 30, 35, 39, 41, 45, 50, 54, 55, 57, 58, and 59 and the most significant bit of the second segment is fed back to bits 67, 68, 72, 78, 79, 80, 84, 88, 90, 95, 98, 99, 103, 104, 105, 109, 113, 118, 121, and 125 and the most significant bit of the third segment is fed back to bits 130, 132, 136, 138, 139, 142, 144, 148, 152, 155, 159, 163, 165, 166, 170, 173, 178, 181, 185, 186, 188, and 190 and the most significant bit of the last segment is fed back to bits 194, 197, 199, 203, 210, 213, 216, 217, 219, 224, 227, 230, 232, 235, 238, 241, 243, and 247 of the input register.
Claim 14
Dependent Claim
36 words
An input register as set forth in claim 12 wherein feed back is XORed with the output of the next previous bit except in the case of bit 0, which is XORed with Test Data Input.
Claim 15
Dependent Claim
35 words
An input register as set forth in claim 12 wherein feedback is XORed with the output of the next previous but except in the case of bit 0, which is XORed with any consistent signal.
Claim 16
Dependent Claim
39 words
An input register as set forth in claim 1 wherein dummy flip-flops are used to increase the number of flip-flops in the register to said predetermined number, and wherein these dummy flip-flops are not connected directly to input pins.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-10 | 1993-01-09 | 1993-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-10 | 1997-01-09 | 1997-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-10 | 2001-01-09 | 2001-07-11 | $7700.00 | Window Closed / Lapsed |