US4855955A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Three transistor high endurance eeprom cell
Assignee: Atmel Corp
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Filing: 1988-04-08
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Granted: 1989-08-08
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Expires: 2008-04-08
Abstract
Abstract The memory cell of the present invention is a three transistor cell, including two floating gate MOS transistors connected in series with a select transistor. The source of the first memory cell floating gate memory transistor is connected to a source of a first potential. Its gate is connected to a first sense line. Its drain is connected to the source of the second memory cell floating gate transistor. The gate of the second memory cell floating gate transistor is connected to a second sense line. The drain of the second memory cell floating gate transistor is connected to the source of a select transistor. The gate of the select transistor is connected to a word line. The source of the select transistor is connected to a bit line. A plurality of memory cells may be connected together as a byte, and may be placed in an array. The gates of the select transistors are connected together. A word line signal which drives the gates of the select transistors also drives the gates of two sense line byte select transistors which enable the sense line signals to appear on only the gates of the memory cell floating gate transistors of the selected byte.
Inventors
- 👤 Dumitru G. Cioaca
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:55
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
159 words
An electrically-erasable programmable read only memory cell, including, a first floating gate MOS transistor having a floating gate and having its source connected to a first potential, and its control gate connected to a first sense line, a second floating gate MOS transistor having a floating gate, the floating gate of said first floating gate MOS transistor being electrically isolated from the floating gate of said second floating gate MOS transistor and the source of said second floating gate MOS transistor connected to the drain of said first floating gate MOS transistor, and the control gate of said second floating gate MOS transistor connected to a second sense line, an MOS select transistor, having its source connected to the drain of said second floating gate MOS transistor, its gate connected to a word line, and its drain connected to a bit line, whereby if one of said floating gate MOS transistors fails, said memory cell will continue to function.
Claim 2
Dependent Claim
159 words
An electrically-erasable programmable read only memory cell, including, a first floating gate MOS transistor having a floating gate and having its source connected to a first potential, and its control gate connected to a first sense line, a second floating gate MOS transistor having a floating gate, the floating gate of said first floating gate MOS transistor being electrically isolated from the floating gate of said second floating gate MOS transistor and the source of said second floating gate MOS transistor connected to the drain of said first floating gate MOS transistor, and the control gate of said second floating gate MOS transistor connected to a second sense line, an MOS select transistor, having its source connected to the drain of said second floating gate MOS transistor, its gate connected to a word line, and its drain connected to a bit line, whereby if one of said floating gate MOS transistors fails, said memory cell will continue to function.
Claim 3
Dependent Claim
291 words
An array of floating gate electrically-erasable programmable read only memory cells, including: a plurality of floating gate electrically-erasable programmable read only memory cells arranged into bytes, each of said cells including a first floating gate MOS transistor having a floating gate and having its source connected to a first potential, and its control gate connected to a first sense line, a second floating gate MOS transistor having a floating gate electrically isolated from the floating gate of said first floating gate MOS transistor and having its source connected to the drain of said first floating gate MOS transistor, and its control gate connected to a second sense line, a MOS select transistor, having its source connected to the drain of said second floating gate MOS transistor, and its gate connected to a word line, a bit line select transistor, associated with each memory cell, and bit line select transistor having its source connected to the drain of said select transistor of the memory cell with which it is associated, its drain connected to a data line, and its gate connected to a Y select line, a word line connected to the gates of all of said select transistors associated with a selected byte, a first array sense line, a second array sense line, a first sense line select transistor, having a drain connected to said first array sense line, a gate connected to said Y select line, and a source connected to a first byte sense line associated with said selected byte, a second sense line select transistor, having a drain connected to said second array sense line, a gate connected to said Y select line, and a source connected to a second byte sense line associated with said selected byte.
Claim 4
Dependent Claim
291 words
An array of floating gate electrically-erasable programmable read only memory cells, including: a plurality of floating gate electrically-erasable programmable read only memory cells arranged into bytes, each of said cells including a first floating gate MOS transistor having a floating gate and having its source connected to a first potential, and its control gate connected to a first sense line, a second floating gate MOS transistor having a floating gate electrically isolated from the floating gate of said first floating gate MOS transistor and having its source connected to the drain of said first floating gate MOS transistor, and its control gate connected to a second sense line, a MOS select transistor, having its source connected to the drain of said second floating gate MOS transistor, and its gate connected to a word line, a bit line select transistor, associated with each memory cell, and bit line select transistor having its source connected to the drain of said select transistor of the memory cell with which it is associated, its drain connected to a data line, and its gate connected to a Y select line, a word line connected to the gates of all of said select transistors associated with a selected byte, a first array sense line, a second array sense line, a first sense line select transistor, having a drain connected to said first array sense line, a gate connected to said Y select line, and a source connected to a first byte sense line associated with said selected byte, a second sense line select transistor, having a drain connected to said second array sense line, a gate connected to said Y select line, and a source connected to a second byte sense line associated with said selected byte.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-07 | 1993-02-06 | 1993-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-07 | 1997-02-06 | 1997-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-07 | 2001-02-06 | 2001-08-08 | $7700.00 | Window Closed / Lapsed |