Information processing system capable of reducing invalid memory operations by detecting an error in a main memory

Claim 2

An information processing system comprising a main memory which has a plurality of addresses and which is accessible by a processor by an access operation carried out in said processor with a preselected address selected from said addresses during said access operation, said information processing system being operable to diagnose an error which might result in said main memory from said access operation, said processor comprising detecting means for detecting occurrence of said error to produce an error signal representative of said occurrence of the error and memory address storage means coupled to said detecting means for memorizing the preselected address on said occurrence of the error, wherein the improvement comprises: address producing means operable on said occurrence of the error and coupled to said detecting means and said memory address storage means for producing not only said preselected address but also an additional address of the addresses that is different from said preselected address to access both said preselected address and said additional address; receiving means for receiving access results of accessing said preselected and said additional addresses; judging means coupled to said receiving means for judging a faulty portion and a normal portion of said main memory in response to said access results to produce a result of judgment; and memory restructuring means coupled to said judging means for restructuring said main memory in response to said result of judgment by isolating said faulty portion from said normal portion.

Claim 3

An information processing system as claimed in claim 1, said main memory comprising first through n-th memory units which have predetermined numbers of said addresses, respectively, consecutively numbered from said first memory unit to said n-th memory unit, where n is an integer greater than unity, wherein said preselected address specifies a preselected one of said first through n-th memory units while said additional address specifies an additional one of said first through n-th memory units that is different from said preselected one of the first through n-th memory units.

Claim 4

An information processing system as claimed in claim 2, wherein said address producing means produces a subsidiary address for specifying a subsidiary one of said first through n-th memory units that is different from said preselected and said additional ones of the memory units.

Claim 5

An information processing system as claimed in claim 3, wherein said address producing means further produces a plurality of local addresses for specifying local ones of said first through n-th memory units that are different from said preselected, said additional, and said subsidiary ones of the memory units.

Claim 6

An information processing system as claimed in claim 1, further comprising: error discriminating means operable on said occurrence of the error and coupled to said judging means for discriminating whether or not the error is caused by said main memory to inform said judging means of said occurrence of the error.

Claim 7

An information processing system comprising a main memory having a plurality of addresses, a plurality of processors each of which is accessible to said main memory by carrying out an access operation with a preselected one of said memory addresses indicated, and an access control device intermediate between said main memory and said processors for controlling said access operation of each of said processors, said main memory comprising a plurality of memory units which can be accessed independently of one another and a common control section coupled to said memory units and said access control device for controlling said plurality of the memory units in common, said preselected memory address being located at a preselected one of said memory units, each of said processors being operable as a request source processor and comprising detecting means for detecting occurrence of an error which might occur on the access operation of each of said processors, error detection signal producing means coupled to said detecting means for producing an error detection signal representative of occurrence of said error, and memory address storage means coupled to said detecting means for storing the preselected one of the memory addresses on occurrence of the error, wherein the improvement comprises: diagnostic address producing means coupled to said error detection signal producing means and said memory address storage means and responsive to said error detection signal for producing a plurality of diagnostic address signals specifying said preselected memory address and at least one additional memory address which is determined in relation to said preselected memory address and which is present in a different one of said memory units from the preselected one of said memory units; memory access means operable on the occurrence of said error and coupled to said diagnostic address producing means for accessing said main memory by the use of said plurality of the diagnostic address signals to make said main memory produce diagnostic results of accessing said main memory by the use of said diagnostic address signals; identifying means responsive to said diagnostic results for identifying a diagnostic error in said diagnostic results to discriminate whether or not the diagnostic error is caused by said main memory; judging means coupled to said error detection signal producing means, said diagnostic address producing means, and said identifying means for judging whether said diagnostic error is caused either by said common control section or by any of said memory units accessed by said diagnostic address signals when said diagnostic error is caused by said main memory to produce a result of judgment; and memory restructuring means coupled to said judging means for restructuring said memory units in response to said result of judgment.

Claim 8

An information processing system comprising a main memory having a plurality of addresses, a plurality of processors each of which is accessible to said main memory by carrying out an access operation with a preselected one of said memory addresses indicated, and an access control device intermediate between said main memory and said processors for controlling said access operation of each of said processors, said main memory comprising a plurality of memory units which can be accessed independently of one another and a common control section coupled to said memory units and said access control device for controlling said plurality of the memory units in common, said preselected memory address being located at a preselected one of said memory units, each of said processors being operable as a request source processor and comprising detecting means for detecting occurrence of an error which might occur on the access operation of each of said processors, error detection signal producing means coupled to said detecting means for producing an error detection signal representative of occurrence of said error, and memory address storage means coupled to said detecting means for storing the preselected one of the memory addresses on occurrence of the error, wherein the improvement comprises: diagnostic address producing means coupled to said error detection signal producing means and said memory address storage means and responsive to said error detection signal for producing a plurality of diagnostic address signals specifying said preselected memory address and at least one additional memory address which is determined in relation to said preselected memory address and which is present in a different one of said memory units from the preselected one of said memory units; memory access means operable on the occurrence of said error and coupled to said diagnostic address producing means for accessing said main memory by the use of said plurality of the diagnostic address signals to make said main memory produce diagnostic results of accessing said main memory by the use of said diagnostic address signals; identifying means responsive to said diagnostic results for identifying a diagnostic error in said diagnostic results to discriminate whether or not the diagnostic error is caused by said main memory; judging means coupled to said error detection signal producing means, said diagnostic address producing means, and said identifying means for judging whether said diagnostic error is caused either by said common control section or by any of said memory units accessed by said diagnostic address signals when said diagnostic error is caused by said main memory to produce a result of judgment; and memory restructuring means coupled to said judging means for restructuring said memory units in response to said result of judgment.