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US4876216A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor integrated circuit manufacturing process providing oxide-filled trench isolation of circuit devices

Assignee: Qualcomm Inc
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Filing: 1988-03-07
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Granted: 1989-10-24
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Expires: 2008-03-07
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Abstract

Abstract In a method of semiconductor integrated circuit manufacture, a manufacturing process improvement provides highly planar, oxide-filled trench isolation of circuit device areas. The process improvement includes formation of a device area covered by a relatively thin insulating layer of oxide by a trenching process that forms a trench adjacent the device area. The thin insulating layer of oxide is extended over the side surface transition between the device area and the trench and then an insulating layer of crystalline dielectric material relatively thicker than the thin insulating layer is applied, which builds the trench at least to the level of the device area. A first layer of photoresist is applied over the thick insulating layer. The portion of the first photoresist layer overlying the device area is photolithographically removed, and then a second layer of photoresist is applied over the first layer; the second layer is applied to a thickness resulting in a relatively planar surface of photoresist overlying the trench and device area. All of the layers overlying the device area are removed by a process which operates toward the substrate surface on which the device area is formed. The removal process removes the first and second photoresist layers, the oxide of the relatively thin layer, and the crystalline dielectric material at substantially the same rate until the device area is expoded. When the device area is exposed, the removal process is terminated. The result provides a device area isolated by an oxide-filled trench, with the surface transition from the device area to the trench oxide being relatively planar.

Inventors

  • 👤 Eric Tobias
  • 👤 Chau-Shiong A. Chen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 18:45
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 257 words
In a process for manufacturing an integrated circuit device on a semiconductor substrate, an improvement for isolating individual circuit elements in said device, comprising the steps of: forming a device area having an upper surface on a surface of said substrate by a trenching process which forms a trench adjacent said device area, said trench having a side surface which extends to said device area; forming a relatively thin insulating layer of oxide covering said device area upper surface, said trench side surface and the floor surface of said trench; applying, over said thin insulating layer, an insulating layer of crystalline dielectric material which is relatively thicker than said thin insulating layer and which fills said trench at least to the level of said device area upper surface; applying a first layer of photoresist over said thicker insulating layer and photolithographically removing the portion of said first layer which overlies said device area; applying a relatively planar second layer of photoresist over said first layer of photoresist; and removing said second layer, said first layer and said relatively thicker insulating layer by means of a removal process in which removal proceeds toward said substrate surface from said second layer and which removes the photoresists of said first and second layers, the oxide of said relatively thin layer and the crystalline dielectric material at substantially the same removal rate, and ceasing said removing when said removal process has progressed to the point at which the level of said device area is reached and said device area is exposed.
Claim 2
Dependent Claim 257 words
In a process for manufacturing an integrated circuit device on a semiconductor substrate, an improvement for isolating individual circuit elements in said device, comprising the steps of: forming a device area having an upper surface on a surface of said substrate by a trenching process which forms a trench adjacent said device area, said trench having a side surface which extends to said device area; forming a relatively thin insulating layer of oxide covering said device area upper surface, said trench side surface and the floor surface of said trench; applying, over said thin insulating layer, an insulating layer of crystalline dielectric material which is relatively thicker than said thin insulating layer and which fills said trench at least to the level of said device area upper surface; applying a first layer of photoresist over said thicker insulating layer and photolithographically removing the portion of said first layer which overlies said device area; applying a relatively planar second layer of photoresist over said first layer of photoresist; and removing said second layer, said first layer and said relatively thicker insulating layer by means of a removal process in which removal proceeds toward said substrate surface from said second layer and which removes the photoresists of said first and second layers, the oxide of said relatively thin layer and the crystalline dielectric material at substantially the same removal rate, and ceasing said removing when said removal process has progressed to the point at which the level of said device area is reached and said device area is exposed.
Claim 3
Dependent Claim 15 words
The method of claim 1 wherein said trench has a depth of substantially 1 micrometer.
Claim 4
Dependent Claim 20 words
The method of claim 1 wherein said relatively thin layer of oxide is from 300 angstroms to 1000 angstroms thick.
Claim 5
Dependent Claim 13 words
The method of claim 3 wherein said relatively thin layer is silicon dioxide.
Claim 6
Dependent Claim 17 words
The method of claim 1 wherein said first and second photoresist layers comprise an organic resist material.

References Cited (Backward Citations)

US4455740A Cited
US4407851A Cited
JPS6039835A Cited
JPS60117753A Cited
US4543706A Cited
US4740480A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-10-23 1993-04-24 1993-10-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-10-23 1997-04-24 1997-10-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-10-23 2001-04-24 2001-10-24 $7700.00 Window Closed / Lapsed

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