US4878233A
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Data pattern synchronizer
Assignee: Advantest Corp
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Filing: 1988-12-09
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Granted: 1989-10-31
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Expires: 2008-12-09
Abstract
Abstract A clock regenerator generates a clock Co synchronized with an input data pattern and a data pattern generator generates a reference data pattern in synchronization with the clock Co. The reference data pattern and the input data pattern are compared by a data disagreement detector to detect disagreement therebetween. The disagreement detection signal thus obtained is frequency divided by a 1/m-frequency divider and its frequency-divided output is further frequency divided by a 1/-n frequency divider. The frequency-divided output of the 1/n-frequency divider is provided to a bistable flip-flop, placing it in one stable state. The logical sum of the output of the flip-flop in the one stable state and the 1/m-frequency divider is obtained, as an inhibit pulse, by an AND gate, and the inhibit pulse is applied to another AND gate to inhibit the passage therethrough of the clock Co to the data pattern generator, delaying the generation of the reference data pattern in the data pattern generator. The 1/m-frequency divider, the 1/n-frequency divider and the flip-flop are reset every k pulses of the clock Co.
Inventors
- 👤 Mishio Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:58
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/042
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
260 words
A data pattern synchronizer comprising: data pattern generating means for generating a reference data pattern in response to a clock synchronized with an input data pattern; data disagreement detecting means which compares, bit by bit, the input data pattern to be measured for its error rate and the reference data pattern and yields a data disagreement detection pulse when the input data pattern and the reference data pattern are not in agreement with each other; first frequency dividing means for frequency dividing the clock down to 1/k, k being a positive integer; second frequency dividing means which is reset by the output pulse of the first frequency dividing means and frequency divides the data disagreement detection pulse down to 1/m, m being a positive integer smaller than k; third frequency dividing means which is reset by the output pulse by the first frequency dividing means and frequency divides the output pulse of the second frequency dividing means down to 1/n, n being selected so that it is smaller than k and m·n<k; flip-flop means which is placed in a first stable state by the output pulse of the third frequency dividing means and in a second stable state by the output pulse of the first frequency dividing means; first gate means for producing an inhibit pulse based on the output pulse of the second frequency dividing means and the first or second stable state of the flip-flop means; and second gate means responsive to the inhibit pulse to inhibit the supply of the clock to the data pattern generating means.
Claim 2
Dependent Claim
260 words
A data pattern synchronizer comprising: data pattern generating means for generating a reference data pattern in response to a clock synchronized with an input data pattern; data disagreement detecting means which compares, bit by bit, the input data pattern to be measured for its error rate and the reference data pattern and yields a data disagreement detection pulse when the input data pattern and the reference data pattern are not in agreement with each other; first frequency dividing means for frequency dividing the clock down to 1/k, k being a positive integer; second frequency dividing means which is reset by the output pulse of the first frequency dividing means and frequency divides the data disagreement detection pulse down to 1/m, m being a positive integer smaller than k; third frequency dividing means which is reset by the output pulse by the first frequency dividing means and frequency divides the output pulse of the second frequency dividing means down to 1/n, n being selected so that it is smaller than k and m·n<k; flip-flop means which is placed in a first stable state by the output pulse of the third frequency dividing means and in a second stable state by the output pulse of the first frequency dividing means; first gate means for producing an inhibit pulse based on the output pulse of the second frequency dividing means and the first or second stable state of the flip-flop means; and second gate means responsive to the inhibit pulse to inhibit the supply of the clock to the data pattern generating means.
Claim 3
Dependent Claim
31 words
The data pattern synchronizer of claim 1, wherein the data disagreement detecting means includes comparing means for comparing the input data pattern and the reference data pattern on a bitwise basis.
Claim 4
Dependent Claim
29 words
The data pattern synchronizer of claim 2, further comprising clock generating means for deriving from the input data pattern the clock of a frequency equal to its bit rate.
Claim 5
Dependent Claim
164 words
The data pattern synchronizer of claim 1, which further comprises clock generating means for generating a first clock of a frequency equal to the bit rate of the input data pattern and a second clock obtained by frequency dividing the first clock down to 1/2 h , h being an integer greater than 1, and wherein the data disagreement detecting means includes demultiplexer means for demultiplexing the input data pattern into 2 h data pattern sequences in synchronization with the first clock, 2 h comparing means each supplied at one input with one of the 2 h data pattern sequences, and logical OR means for ORing the compared outputs of the comparing means and yielding the logical OR as the data disagreement detection pulse, and wherein the data pattern generating means generates, in synchronization with the second clock, 2 h reference data patterns sequentially displaced apart in phase but having the same waveform and applies them to the other inputs of the comparing means.
Claim 6
Dependent Claim
23 words
The data pattern synchronizer of claim 4, wherein the reference data patterns generated by the data pattern generating means are pseudo-random data patterns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-30 | 1993-05-01 | 1993-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-30 | 1997-05-01 | 1997-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-30 | 2001-05-01 | 2001-10-31 | $7700.00 | Window Closed / Lapsed |