Debugging microprocessor

Claim 2

A debugging processor comprising: a bus control unit for transmitting and receiving data, address and control signals to and from an external microprocessor development support system, an instruction execution unit coupled to transmit and receive data and address signals to and from the bus control unit and also to receive an instruction code from the bus control unit for executing the given instruction, said instruction execution unit having a fixed branch destination address for a debug interrupt operation, an interrupt control unit coupled to receive at least a debug interrupt from the external microprocessor development support system and for notifying the instruction execution unit of an interrupt request, and a debug interrupt response control unit having a priority higher than that of the interrupt control unit, said execution unit operating in response to the notification of the interrupt request from the interrupt control unit to instruct the bus control unit to start an internal information save operation after there have been completed an execution of an instruction which is being executed when the instruction execution unit is notified of the interrupt request, the execution unit also operating to notify the debug interrupt response control unit of the instruction of the internal information save operation to the bus control unit, said bus control unit responding to the instruction of the internal information save operation from the execution unit to output a signal indicative of an execution of a bus cycle for the internal information save operation to the debug interrupt response control unit, in synchronism with a bus cycle of the bus control unit, after there has been completed a bus cycle which is being executed when the start of the internal information save operation of the execution unit is detected, so that the debug interrupt response control unit operates to generate to the external microprocessor development support system a debug interrupt response signal which becomes active only during a period of save operation for the internal information, and thereafter, the execution unit operating to move into an operation for the debug interrupt.

Claim 3

A microprocessor development support system coupled with a first memory external of the microprocessor development support system and storing a program to be debugged and also coupled to receive a non-maskable interrupt from a device external of the microprocessor development support system, comprising: a controller coupled to the first memory through an internal access bus, said controller generating a break request, a second memory storing a debugging program and being coupled to the internal access bus, a third memory coupled to the internal access bus so as to save a necessary information, and a debugging microprocessor selectively coupled to one of the first memory and the second memory so as to execute the program to be debugged and the debugging program, said debugging microprocessor receiving the non-maskable interrupt and the break request independently of each other for generating a debug interrupt response signal to the controller and the second and third memories, said debugging microprocessor operating in such a manner that when the non-maskable interrupt and the debug interrupt are concurrently generated, the debugging microprocessor is firstly operable to read a branch destination address for a non-maskable interrupt operation so as to write the branch destination address for the non-maskable interrupt operation to a program counter, and then is operable to save the content of the program counter to the third memory while outputting to the controller a debug interrupt response signal which becomes active only during a period of save operation for the program counter, and thereafter, the execution unit operating to move into an operation for the debug interrupt.

Claim 4

A microprocessor development support system coupled with a first memory external of the microprocessor development support system and storing a program to be debugged and also coupled to receive a non-maskable interrupt from a device external of the microprocessor development support system, comprising: a controller coupled to the first memory through an internal access bus, said controller generating a break request, a second memory storing a debugging program and being coupled to the internal access bus, a third memory coupled to the internal access bus so as to save a necessary information, and a debugging microprocessor selectively coupled to one of the first memory and the second memory so as to execute the program to be debugged and the debugging program, said debugging microprocessor receiving the non-maskable interrupt and the break request independently of each other for generating a debug interrupt response signal to the controller and the second and third memories, said debugging microprocessor operating in such a manner that when the non-maskable interrupt and the debug interrupt are concurrently generated, the debugging microprocessor is firstly operable to read a branch destination address for a non-maskable interrupt operation so as to write the branch destination address for the non-maskable interrupt operation to a program counter, and then is operable to save the content of the program counter to the third memory while outputting to the controller a debug interrupt response signal which becomes active only during a period of save operation for the program counter, and thereafter, the execution unit operating to move into an operation for the debug interrupt.

Claim 5

A system claimed in claim 4 wherein the debugging processor includes a bus control unit for transmitting and receiving data to and from an external, an instruction execution unit receiving an instruction code from the bus control unit for executing the given instruction, an interrupt control unit receiving the non-maskable interrupt and the break request for notifying the instruction execution unit of an interrupt request, and a debug interrupt response control unit having a fixed branch destination address and coupled to the execution unit and the bus control unit so as to generate the debug interrupt response signal.

Claim 6

A system claimed in claim 3 wherein the interrupt control unit receives a non-maskable interrupt and a debug interrupt independently of each other, and when the non-maskable interrupt and the debug interrupt are concurrently generated, the interrupt control unit firstly notifies the execution unit that the non-maskable interrupt has been requested, and thereafter, notifies the execution unit that the debug interrupt has been requested.

Claim 7

A system claimed in claim 4 wherein when the execution unit is notified that the non-maskable interrupt has been requested, the execution unit reads the content of a memory location storing a branch destination address for a non-maskable interrupt operation, and when the execution unit is thereafter immediately notified that the debug interrupt has been requested, the execution unit performs the save operation for a program counter and a program status word, and then, moves to the operation of the debug interrupt.

Claim 8

A debugging microprocessor comprising a bus control unit for transmitting and receiving data, address and control signals to and from an external microprocessor development support system, comprising: an instruction execution unit coupled to transmit and receive data and address signals to and from the bus control unit and also to receive an instruction code from the bus control unit for executing the given instruction, said instruction execution unit having a fixed branch destination address for a debug interrupt operation, an interrupt control unit coupled to receive a non-maskable interrupt and a debug interrupt independently of each other for notifying the instruction execution unit of an interrupt request, said debug interrupt being supplied from the external microprocessor development support system, and a debug interrupt response control unit having a priority higher than that of the interrupt control unit, said interrupt control unit operating in such a manner that when the non-maskable interrupt and the debug interrupt are concurrently generated, the interrupt control unit firstly notifies the execution unit that the non-maskable interrupt has been requested, and thereafter, immediately notifies the execution unit that the debug interrupt has been requested, said execution unit operating in response to the notification of the non-maskable interrupt request to read a branch destination address for a non-maskable interrupt operation so as to write the branch destination address for the non-maskable interrupt operation to a program counter, and operating in response to the notification of the debug interrupt request to instruct the bus control unit to start a program counter and program status word save operation, after the writing of the branch destination address for the non-maskable interrupt operation to the program counter has been completed, said execution unit also operating to notify the debug interrupt response control unit of the instruction of the program counter and program status word save operation to the bus control unit, the bus control unit responding to the instruction of the program counter and program status word save operation from the execution unit to output a signal indicative of an execution of a bus cycle for the program counter and program status word save operation to the debug interrupt response control unit, in synchronism with a bus cycle of the bus control unit, after there has been completed a bus cycle which is being executed when the start of the program counter and program status word save operation of the execution unit is detected, so that the debug interrupt response control unit operates to generate to the external microprocessor development support system a debug interrupt response signal which becomes active only during a period of save operation for the program counter and program status word, and thereafter, the execution unit operating to move into an operation for the debug interrupt.

Claim 9

A debugging microprocessor comprising a bus control unit for transmitting and receiving data, address and control signals to and from an external microprocessor development support system, comprising: an instruction execution unit coupled to transmit and receive data and address signals to and from the bus control unit and also to receive an instruction code from the bus control unit for executing the given instruction, said instruction execution unit having a fixed branch destination address for a debug interrupt operation, an interrupt control unit coupled to receive a non-maskable interrupt and a debug interrupt independently of each other for notifying the instruction execution unit of an interrupt request, said debug interrupt being supplied from the external microprocessor development support system, and a debug interrupt response control unit having a priority higher than that of the interrupt control unit, said interrupt control unit operating in such a manner that when the non-maskable interrupt and the debug interrupt are concurrently generated, the interrupt control unit firstly notifies the execution unit that the non-maskable interrupt has been requested, and thereafter, immediately notifies the execution unit that the debug interrupt has been requested, said execution unit operating in response to the notification of the non-maskable interrupt request to read a branch destination address for a non-maskable interrupt operation so as to write the branch destination address for the non-maskable interrupt operation to a program counter, and operating in response to the notification of the debug interrupt request to instruct the bus control unit to start a program counter and program status word save operation, after the writing of the branch destination address for the non-maskable interrupt operation to the program counter has been completed, said execution unit also operating to notify the debug interrupt response control unit of the instruction of the program counter and program status word save operation to the bus control unit, the bus control unit responding to the instruction of the program counter and program status word save operation from the execution unit to output a signal indicative of an execution of a bus cycle for the program counter and program status word save operation to the debug interrupt response control unit, in synchronism with a bus cycle of the bus control unit, after there has been completed a bus cycle which is being executed when the start of the program counter and program status word save operation of the execution unit is detected, so that the debug interrupt response control unit operates to generate to the external microprocessor development support system a debug interrupt response signal which becomes active only during a period of save operation for the program counter and program status word, and thereafter, the execution unit operating to move into an operation for the debug interrupt.