Method of manufacturing a semiconductor device, in which metal silicide is provided in a self-registered manner

Claim 1

A method of manufacturing a semiconductor device including an insulated gate field effect transistor comprising the steps of (a) providing a layer of silicon oxide on a surface of a semiconductor substrate of monocrystalline silicon, (b) covering said layer of silicon oxide with a layer of doped polycrystalline silicon, (c) forming a mask containing silicon nitride on said layer of doped polycrystalline silicon, (d) etching said layer of doped polycrystalline silicon to said layer of silicon oxide using said mask as an etching mask to form a gate electrode of said doped polycrystalline silicon under said etching mask, (e) maintaining said etching mask on said gate electrode, (f) forming source and drain zones in said monocrystalline silicon of said semiconductor substrate using said etching mask, (g) forming edge isolation parts about sides of said gate electrode by the steps of covering said surface with a further layer of silicon oxide and anisotropically etching said further layer, (h) removing said etching mask by exposing said polycrystalline silicon of said gate electrode, and exposing said source and drain zones by removing any remaining layer of silicon oxide, (i) covering said gate electrode and said source and drain zones with a layer of metal-containing material, (j) forming a metal silicide from said metal-containing layer contacting said gate electrode and said source and drain zones by heating and reacting said metal-containing layer with said polycrystalline silicon of said gate electrode and with said monocrystalline silicon of said source and drain zones, and (k) removing any parts of said metal-containing layer free of contact with said polycrystalline silicon gate electrode or with said monocrystalline silicon source and drain zones.

Claim 2

A method of manufacturing a semiconductor device including an insulated gate field effect transistor comprising the steps of (a) providing a layer of silicon oxide on a surface of a semiconductor substrate of monocrystalline silicon, (b) covering said layer of silicon oxide with a layer of doped polycrystalline silicon, (c) forming a mask containing silicon nitride on said layer of doped polycrystalline silicon, (d) etching said layer of doped polycrystalline silicon to said layer of silicon oxide using said mask as an etching mask to form a gate electrode of said doped polycrystalline silicon under said etching mask, (e) maintaining said etching mask on said gate electrode, (f) forming source and drain zones in said monocrystalline silicon of said semiconductor substrate using said etching mask, (g) forming edge isolation parts about sides of said gate electrode by the steps of covering said surface with a further layer of silicon oxide and anisotropically etching said further layer, (h) removing said etching mask by exposing said polycrystalline silicon of said gate electrode, and exposing said source and drain zones by removing any remaining layer of silicon oxide, (i) covering said gate electrode and said source and drain zones with a layer of metal-containing material, (j) forming a metal silicide from said metal-containing layer contacting said gate electrode and said source and drain zones by heating and reacting said metal-containing layer with said polycrystalline silicon of said gate electrode and with said monocrystalline silicon of said source and drain zones, and (k) removing any parts of said metal-containing layer free of contact with said polycrystalline silicon gate electrode or with said monocrystalline silicon source and drain zones.