Semiconductor memory device with staggered sense amplifiers

Claim 1

A semiconductor memory device of an open bit line configuration, comprising: a plurality of memory cells arranged in rows and columns; a plurality of periodically spaced, vertically-extending word lines for performing row selection of said plurality of memory cells; a plurality of sense amplifiers arranged in rows and columns, each of said sense amplifiers respectively having an open bit line composed of a left bit line portion and a right bit line portion, said left and right bit line portions extending horizontally in opposite directions from the respective said sense amplifier for performing column selection of said plurality of memory cells; the sense amplifiers within each column being separated from each other by a predetermined vertical distance and the sense amplifiers within each row being separated from each other at a periodic spacing; each of said open bit lines in corresponding rows in alternate columns being at substantially the same height, and each of said open bit lines in adjacent columns in corresponding adjacent rows being staggered in a vertical direction relative to each other by about half said predetermined vertical distance the left bit line portions of the sense amplifiers which are disposed in a single column overlapping in a vertical direction with the right bit line portions of the sense amplifiers which are disposed in an adjacent column; each of said left and right bit line portions of the sense amplifiers which are disposed in a single column terminating such that they do not overlap in the vertical direction with the sense amplifiers which are disposed in an adjacent column.