Patent US4594181A successfully refreshed from Google Patents.
Patent US4908531A successfully refreshed from Google Patents.
US4908531A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithic active isolator
Assignee: Pacific Monolithics Inc
•
Filing: 1988-09-19
•
Granted: 1990-03-13
•
Expires: 2008-09-19
Abstract
Abstract A push-pull monolithic active isloator having a pair of MESFETs in common-gate and common-drain (source follower), parallel configuration. These two FETs are the same size and a diode is inserted between the gate of the source follower and the source of the common-gate FET. A D.C. blocking capacitor is included at the output. Another FET is coupled between the input and ground and responsive to a control signal to vary the current in a biasing resistor between the drain and gate of the source follower.
Inventors
- 👤 Allen F. Podell
- 👤 Sanjay B. Moghe
- 👤 Fazal Ali
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:58
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6871
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
84 words
An active isolator circuit for electrically isolating an input terminal from an output terminal comprising: a common-gate transistor means having a gate means coupled to ground, a source means coupled to the input terminal, and a drain means coupled to the output terminal; and a source-follower transistor means having a gate means coupled to said source means of said common-gate transistor means, a drain means coupled to a voltage source, and a source means coupled to said drain means of said common-gate transistor means.
Claim 2
Dependent Claim
84 words
An active isolator circuit for electrically isolating an input terminal from an output terminal comprising: a common-gate transistor means having a gate means coupled to ground, a source means coupled to the input terminal, and a drain means coupled to the output terminal; and a source-follower transistor means having a gate means coupled to said source means of said common-gate transistor means, a drain means coupled to a voltage source, and a source means coupled to said drain means of said common-gate transistor means.
Claim 3
Dependent Claim
51 words
A circuit according to claim 1 further comprising level shift means posed between said gate means of said source-follower transistor means and said source means of said common-gate transistor means, said level shift means providing a minimum voltage between said gate means and said source means of said source-follower transistor means.
Claim 4
Dependent Claim
18 words
A circuit according to claim 1 wherein both of said transistor means are high electron mobility transistors (HEMTs).
Claim 5
Dependent Claim
15 words
A circuit according to claim 1 wherein both of said transistor means are unipolar transistors.
Claim 6
Dependent Claim
11 words
A circuit according to claim 4 wherein said transistors are MESFETs.
Claim 7
Dependent Claim
44 words
A circuit according to claim 1 further comprising means for biasing said common-gate transistor means and said source-follower transistor means in a manner maintaining a minimum voltage level between said gate of said source-follower transistor means and said source of said common-gate transistor means.
Claim 8
Dependent Claim
52 words
A circuit according to claim 6 characterized by an input impedance at the input terminal and an output impedance at the output terminal, wherein said biasing means is responsive to a control signal for varying the bias of said source-follower transistor means, and thereby the input and output impedances of said circuit.
Claim 9
Dependent Claim
57 words
A circuit according to claim 7 wherein said biasing means comprises biasing impedance means posed between said gate means and drain means of said source-follower transistor means, and current source means coupled to said gate means of said source-follower transistor means responsive to the control signal for varying the magnitude of the current in said impedance means.
Claim 10
Dependent Claim
19 words
A circuit according to claim 1 wherein said transistor means are configured for single-ended operation of said isolator circuit.
Claim 11
Dependent Claim
26 words
A circuit according to claim 1 further comprising second ones of said common-gate and source-follower transistor means configured to provide push-pull operation of said isolator circuit.
Claim 12
Dependent Claim
89 words
An active isolator circuit for electrically isolating an input terminal from an output terminal comprising: a common-gate MESFET having a gate coupled to ground, a source coupled to the input terminal, and a drain coupled to the output terminal; a source-follower MESFET having a gate coupled to said source of said common-gate MESFET, a drain coupled to a voltage source, and a source coupled to said drain of said common-gate MESFET; and a diode posed between said source of said common-gate MESFET and said gate of said source-follower MESFET.
Claim 13
Dependent Claim
89 words
An active isolator circuit for electrically isolating an input terminal from an output terminal comprising: a common-gate MESFET having a gate coupled to ground, a source coupled to the input terminal, and a drain coupled to the output terminal; a source-follower MESFET having a gate coupled to said source of said common-gate MESFET, a drain coupled to a voltage source, and a source coupled to said drain of said common-gate MESFET; and a diode posed between said source of said common-gate MESFET and said gate of said source-follower MESFET.
Claim 14
Dependent Claim
70 words
A circuit according to claim 11 further comprising a biasing resistor between the voltage source and said gate of said source-follower MESFET, and a current-source MESFET having a drain coupled to said source of said common-gate MESFET, a source coupled to ground, and a gate responsive to a control signal for varying the current in said biasing resistor, and thereby the bias voltage on said gate of said source-follower MESFET.
References Cited (Backward Citations)
US3392341A
Cited
US4492883A
Cited
US4511815A
Cited
US4633097A
Cited
US4679010A
Cited
US4691129A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-12 | 1993-09-11 | 1994-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-12 | 1997-09-11 | 1998-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-12 | 2001-09-11 | 2002-03-13 | $7700.00 | Window Closed / Lapsed |