Abstract The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination. After the polysilicon gate has been delineated, the sloped sidewalls of the field oxide are removed (by anisotropic etching), so that the sidewalls of the apertures or windows of the field oxide layer will be perpendicular to the planar surface of the substrate, thus facilitating proper formation of dielectric (oxide) spacers therealong, which thereby provide separation between contact materials and the junction created by shallow ion implantation of dopants through the field oxide aperture.
A semiconductor device comprising: a semiconductor body having a planar surface; an insulator layer disposed on said planar surface of said semiconductor body and having an aperture therein defining a sidewall of said insulator layer and exposing a portion of said planar surface of said semiconductor body; a layer of conductive material extending from the top surface of said insulator layer into the aperture therein so as to overlie a portion of the exposed planar surface of said semiconductor body; and wherein that portion of the sidewall of said insulator layer defining said aperture over which said layer of conductive material extends has a tapered thickness to said planar surface, such that the thinnest portion of the tapered sidewall of said insulator layer is at the planar surface of said semiconductor body, and that portion of the sidewall of said insulator layer other than that portion of the sidewall of said insulator layer over which said layer of conductive material extends is effectively vertical with respect to said planar surface, and further including a thin dielectric layer disposed on said portion of the exposed planar surface of said semiconductor body over which said layer of conductive material lies, said layer of conductive material being contiguous with the tapered thickness portion of the sidewall of said insulator layer and with the top surface of said dielectric layer, and further comprising insulator spacers disposed on the planar surface of said substrate exposed by the aperture in said insulator layer so as to be contiguous with the vertical sidewall of said insulator layer and sidewall of said layer of conductive material.
Claim 2
Dependent Claim
268 words
A semiconductor device comprising: a semiconductor body having a planar surface; an insulator layer disposed on said planar surface of said semiconductor body and having an aperture therein defining a sidewall of said insulator layer and exposing a portion of said planar surface of said semiconductor body; a layer of conductive material extending from the top surface of said insulator layer into the aperture therein so as to overlie a portion of the exposed planar surface of said semiconductor body; and wherein that portion of the sidewall of said insulator layer defining said aperture over which said layer of conductive material extends has a tapered thickness to said planar surface, such that the thinnest portion of the tapered sidewall of said insulator layer is at the planar surface of said semiconductor body, and that portion of the sidewall of said insulator layer other than that portion of the sidewall of said insulator layer over which said layer of conductive material extends is effectively vertical with respect to said planar surface, and further including a thin dielectric layer disposed on said portion of the exposed planar surface of said semiconductor body over which said layer of conductive material lies, said layer of conductive material being contiguous with the tapered thickness portion of the sidewall of said insulator layer and with the top surface of said dielectric layer, and further comprising insulator spacers disposed on the planar surface of said substrate exposed by the aperture in said insulator layer so as to be contiguous with the vertical sidewall of said insulator layer and sidewall of said layer of conductive material.
Claim 3
Dependent Claim
27 words
A semiconductor device according to claim 1, wherein said insulator layer comprises a field oxide layer and said layer of conductive material comprises a layer of polysilicon.