Patent US4910049A successfully refreshed from Google Patents.
US4910049A
Expired / Lapsed
US
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Conditioning a dielectric substrate for plating thereon
Assignee: International Business Machines Corp
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Filing: 1986-12-15
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Granted: 1990-03-20
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Expires: 2006-12-15
Abstract
Abstract A dielectric substrate is conditioned for plating from an electroless metal plating bath by providing the surface or surfaces of the substrate that are to be plated with semiconductor material whereby the semiconductor material, in the case of n-type material, exhibits energy band where the valence band is equal to or higher than and, in the case of p-type material, exhibits energy band where the valence band is equal to or lower than the redox potential of the metallic ions in the electroless plating bath that are to be deposited as metal on the substrate.
Inventors
- 👤 Perminder S. Bindra
- 👤 Donald F. Canaperi
- 👤 Allan P. David
- 👤 David N. Light
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:47
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/10; H05K3/18; H05K3/181; C; C23; C23C; C23C18/00; C23C18/16; C23C18/18; C23C18/1851; C23C18/1872; C23C18/1886; C23C18/1893
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
136 words
Process for plating a dielectric substrate which comprises: providing the surface of said substrate that is to be subsequently plated with particles of semiconductor material; wherein said particles are included during the formation of said substrate by lamination and wherein; said semiconductor material in the case of n-type material exhibits an energy band where the valence band is at least equal to or higher than and, in the case of p-type material, exhibits an energy band where the valence band is at least equal to or lower than the redox potential of the metallic ions in an electroless metal plating bath that are to be subsequently plated as metal on said dielectric substrate; and then contacting with an electroless metal plating bath containing said metallic ions, thereby depositing said metal on said surfaces of said substrate.
Claim 2
Dependent Claim
136 words
Process for plating a dielectric substrate which comprises: providing the surface of said substrate that is to be subsequently plated with particles of semiconductor material; wherein said particles are included during the formation of said substrate by lamination and wherein; said semiconductor material in the case of n-type material exhibits an energy band where the valence band is at least equal to or higher than and, in the case of p-type material, exhibits an energy band where the valence band is at least equal to or lower than the redox potential of the metallic ions in an electroless metal plating bath that are to be subsequently plated as metal on said dielectric substrate; and then contacting with an electroless metal plating bath containing said metallic ions, thereby depositing said metal on said surfaces of said substrate.
Claim 3
Dependent Claim
49 words
The process of claim 1 wherein said semiconductor material is n-type material that exhibits an energy band where the valence band is higher than the redox potential of the metallic ions in said electroless metal plating bath that are to be subsequently plated as metal on said dielectric substrate.
Claim 4
Dependent Claim
49 words
The process of claim 1 wherein said semiconductor material is p-type material that exhibits an energy band where the valence band is lower than the redox potential of the metallic ions in said electroless metal plating bath that are to be subsequently plated as metal on said dielectric substrate.
Claim 5
Dependent Claim
13 words
The process of claim 1 wherein said dielectric substrate is an epoxy-containing substrate.
Claim 6
Dependent Claim
12 words
The process of claim 1 wherein said metallic ions are copper ions.
Claim 7
Dependent Claim
12 words
The process of claim 1 wherein said metallic ions are palladium ions.
Claim 8
Dependent Claim
12 words
The process of claim 1 wherein said semiconductor material is doped silicon.
Claim 9
Dependent Claim
12 words
The process of claim 5 wherein said semiconductor material is doped silicon.
Claim 10
Dependent Claim
19 words
The process of claim 1 wherein the particle size of said semiconductor particles is less than about 21/2 micron.
Claim 11
Dependent Claim
16 words
The process of claim 1 wherein the particle size of said particles is about 0.5-2 microns.
Claim 12
Dependent Claim
17 words
The process of claim 1 wherein said substrate includes through-holes having said particles on the surfaces thereof.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-19 | 1993-09-18 | 1994-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-19 | 1997-09-18 | 1998-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-19 | 2001-09-18 | 2002-03-20 | $7700.00 | Window Closed / Lapsed |