US4912709A
Expired / Lapsed
US
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Flexible VLSI on-chip maintenance and test system with unit I/O cell design
Assignee: Control Data Corp
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Filing: 1987-10-23
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Granted: 1990-03-27
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Expires: 2007-10-23
Abstract
Abstract This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.
Inventors
- 👤 Judy L. Teske
- 👤 Daniel J. Baxter
- 👤 Don A. Daane
- 👤 Brian D. Borchers
- 👤 David H. Allen
- 👤 Michael F. Maas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:08
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G01R31/318538
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
167 words
A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal inputs and outputs go through unit I/O cells comprising: output buffer means, connected to provide output from the on-chip circuits to chip pins; input buffer means, connected to provide input from chip means to the on-chip circuits; and an output register and a core logic, wherein the output buffer is connected to selectively receive input either from said output register or directly from core logic; wherein the output register is a serial shift register having the data output from each less significant bit fed forward into each next more significant bit during serial shift, and wherein each fed forward signal is selectively disablable so that each said next more significant bit receives instead said fed forward signal logically XORed with one input signal bit from the core logic for each fed forward signal and wherein the most significant bit is fed back into the least significant bit, forming a ring.
Claim 2
Dependent Claim
167 words
A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal inputs and outputs go through unit I/O cells comprising: output buffer means, connected to provide output from the on-chip circuits to chip pins; input buffer means, connected to provide input from chip means to the on-chip circuits; and an output register and a core logic, wherein the output buffer is connected to selectively receive input either from said output register or directly from core logic; wherein the output register is a serial shift register having the data output from each less significant bit fed forward into each next more significant bit during serial shift, and wherein each fed forward signal is selectively disablable so that each said next more significant bit receives instead said fed forward signal logically XORed with one input signal bit from the core logic for each fed forward signal and wherein the most significant bit is fed back into the least significant bit, forming a ring.
Claim 3
Dependent Claim
42 words
In a VLSI circuit/ as set forth in claim 1 and having an input register; I/O cells as set forth in claim 1, wherein said input buffer can selectively provide input to core logic or to an input register, or to both.
Claim 4
Dependent Claim
35 words
In a VLSI circuit as set forth in claim 2, I/O cells as set forth in claim 2 wherein the core logic can selectively receive input from the input register or from the input buffer.
Claim 5
Dependent Claim
30 words
In a VLSI circuit as set forth in claim 3, I/O cells as set forth in claim 3 wherein said selectivity is controlled by signals supplied by a control register.
Claim 6
Dependent Claim
30 words
In a VLSI circuit as set forth in claim 2, I/O cells as set forth in claim 2 wherein said selectivity is controlled by signals supplied by a control register.
Claim 7
Dependent Claim
35 words
In a VLSI circuit, as set forth in claim 1 and having a control register; I/O cells as set forth in claim 1, wherein said selectivity is controlled by signals supplied by said control register.
Claim 8
Dependent Claim
22 words
In a VLSI circuit as set forth in claim 6 wherein said control register has only one data input from a pin.
Claim 9
Dependent Claim
173 words
A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal outputs and outputs go unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; an input buffer means, connected to provide input from chip pins to the on-chip circuits; an output register and a core logic, wherein the output buffer is connected to selectively receive input either from said output register or directly from said core logic; a control register, wherein said selectivity is controlled by signals supplied by said control register, said control register having only one data input from a pin; and a system clock input separated so as to be provided as a CLK 2 signal to the input register and the output register, and as a CLK 1 signal to the control register, and a disablement means provided to selectively disable the CLK 2 signal to allow the control register to be clocked without clocking either the input register or the output register.
Claim 10
Dependent Claim
173 words
A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal outputs and outputs go unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; an input buffer means, connected to provide input from chip pins to the on-chip circuits; an output register and a core logic, wherein the output buffer is connected to selectively receive input either from said output register or directly from said core logic; a control register, wherein said selectivity is controlled by signals supplied by said control register, said control register having only one data input from a pin; and a system clock input separated so as to be provided as a CLK 2 signal to the input register and the output register, and as a CLK 1 signal to the control register, and a disablement means provided to selectively disable the CLK 2 signal to allow the control register to be clocked without clocking either the input register or the output register.
Claim 11
Dependent Claim
101 words
A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; an input buffer means, connected to provide input from chip pins to the on-chip circuits; and at least one signal registration means having at least two outputs, and adapted to receive a mode select signal from off-chip and configured to pass said mode select signal with clocking on one of said outputs and earlier, without clocking, on the other output.
Claim 12
Dependent Claim
101 words
A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; an input buffer means, connected to provide input from chip pins to the on-chip circuits; and at least one signal registration means having at least two outputs, and adapted to receive a mode select signal from off-chip and configured to pass said mode select signal with clocking on one of said outputs and earlier, without clocking, on the other output.
Claim 13
Dependent Claim
48 words
The VLSI circuit of claim 9 further including certain predetermined flip-flops for providing a set-up condition to achieve a particular state for the functioning of the chip wherein said earlier output is connected to provide a set-up signal to said predetermined filp-flops prior to receiving said clocked output.
Claim 14
Dependent Claim
104 words
A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; an input buffer means, connected to provide input from chip pins to the on-chip circuits; and at least one signal registration means having at least two outputs, and adapted to receive a test enable signal from off-chip, said registration means being configured to pass said test enable signal with clocking on one of said outputs and earlier, without clocking, on the other output.
Claim 15
Dependent Claim
104 words
A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; an input buffer means, connected to provide input from chip pins to the on-chip circuits; and at least one signal registration means having at least two outputs, and adapted to receive a test enable signal from off-chip, said registration means being configured to pass said test enable signal with clocking on one of said outputs and earlier, without clocking, on the other output.
Claim 16
Dependent Claim
48 words
The VLSI circuit of claim 11 further including certain predetermined flip-flops for providing a set-up condition to achieve a particular state for the functioning of the chip wherein said earlier output is connected to provide a set-up signal to said predetermined flip-flops prior to receiving said clocked output.
Claim 17
Dependent Claim
121 words
A VLSI circuit having a built-in test and maintenance system wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; and input buffer means, connected to provide input from chip pins to the on-chip circuits; and a system clock input separated so as to be provided as a CLK 2 signal to the input register and the output register, and as a CLK 1 signal to the control register, and wherein a disablement means is provided to selectively disable the CLK 1 signal to allow the input and output registers to be serially loaded and unloaded without affecting the control register.
Claim 18
Dependent Claim
121 words
A VLSI circuit having a built-in test and maintenance system wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; and input buffer means, connected to provide input from chip pins to the on-chip circuits; and a system clock input separated so as to be provided as a CLK 2 signal to the input register and the output register, and as a CLK 1 signal to the control register, and wherein a disablement means is provided to selectively disable the CLK 1 signal to allow the input and output registers to be serially loaded and unloaded without affecting the control register.
Claim 19
Dependent Claim
103 words
A VLSI circuit having a built-in test and maintenance system wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; and input buffer means, connected to provide input from chip pins to the on-chip circuits; and a test data output pin selectively connectable to serially provided data from the core logic area, such as data from a scan path, or from the test data input and these may be logically XORed with output from the output register, through a test data output register.
Claim 20
Dependent Claim
103 words
A VLSI circuit having a built-in test and maintenance system wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; and input buffer means, connected to provide input from chip pins to the on-chip circuits; and a test data output pin selectively connectable to serially provided data from the core logic area, such as data from a scan path, or from the test data input and these may be logically XORed with output from the output register, through a test data output register.
Claim 21
Dependent Claim
104 words
A VLSI circuit having a built-in test and maintenance system wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; and input buffer means, connected to provide input from chip pins to the on-chip circuits; and an input register, a test data input register and a core logic, wherein a shared input pin provides data to the test data input register for serially providing input data to the core logic and identical data to the input register, such as data to a scan path.
Claim 22
Dependent Claim
104 words
A VLSI circuit having a built-in test and maintenance system wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising: an output buffer means, connected to provide output from the on-chip circuits to chip pins; and input buffer means, connected to provide input from chip pins to the on-chip circuits; and an input register, a test data input register and a core logic, wherein a shared input pin provides data to the test data input register for serially providing input data to the core logic and identical data to the input register, such as data to a scan path.
References Cited (Backward Citations)
US4670877A
Cited
US4594711A
Cited
US4601033A
Cited
US4601034A
Cited
US4764926A
Cited
US4701916A
Cited
US4701920A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |