Nonvolatile semiconductor memory

Claim 1

A nonvolatile semiconductor memory comprising: a substrate of a first conductivity type; first, second, and third diffusion layers, of a second conductivity type, formed in said substrate; a first channel region formed in that portion of said substrate which extends between said first and second diffusion layers; a second channel region formed in that portion of said substrate which extends between said second and third diffusion layers; a floating gate electrode formed above said first channel region, part of said floating gate electrode being formed on a thin insulating film formed on said second diffusion layer; a control gate electrode formed above said floating gate electrode; a gate electrode formed above said second channel region; a control gate line for applying a first voltage to said control gate electrode in a data erase mode, and for applying a second voltage, lower than the first voltage, to said control gate electrode in a data write mode and a data read mode; a selection gate line for applying the first voltage to said gate electrode in the date erase mode and data write mode, and for applying a third voltage, which is lower than the first voltage and higher than the second voltage, to said gate electrode in the data read mode; a write line for applying the second voltage to said third diffusion layer in the data erase mode and the data read mode, and for applying the first voltage to said third diffusion layer in the data write mode; and a read line for applying the second voltage to said first diffusion layer in the data erase mode, and for applying the third voltage to said first diffusion layer in the data write mode and the data read mode.