Patent US4195346A successfully refreshed from Google Patents.
Patent US4914581A successfully refreshed from Google Patents.
US4914581A
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Method and apparatus for explicitly evaluating conditions in a data processor
Assignee: NXP USA Inc
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Filing: 1987-10-26
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Granted: 1990-04-03
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Expires: 2007-10-26
Abstract
Abstract In a data processor, the conditions associated with an operand are evaluated only in response to the execution of a special instruction. The results of this evaluation is provided as a result operand and stored in a general purpose destination register. The evaluated conditions are each provided in discrete form, that is, unencoded, rather than in encoded form.
Inventors
- 👤 Yoav Talgam
- 👤 Mitch K. Alsup
- 👤 James A. Klingshirn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:53
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/30094
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
239 words
A method for comparing a first operand to a second operand comprising the steps of: EXCLUSIVE ORing the first operand and the second operand; subtracting the first operand from the second operand to provide a signed difference; generating a first set of condition codes comprising: ZERO (Z) if the first and second operands are logically identical CARRY (C) if the second operand is larger than the first operand; and SIGN (S) if the difference is positive; and logically combining the first set of condition codes to produce a second set of condition codes, whereby said second set of condition codes represents a logical truth value of the combination of each of a number of different logical predicates, said second set of condition codes comprising: Equal (EQ) if the first operand is equal to the second operand; Not Equal (NE) if the first operand is not equal to the second operand; Greater Than (GT) if the first operand is greater than the second operand; Greater than or Equal (GE) if the first operand is greater than the second operand; Less than or Equal (LE) if the first operand is less than or equal to the second operand; and providing the second set condition codes, as respective bits of a data operand, to any one of a predetermined number of data registers, whereby execution of a subsequent explicit evaluate instruction will not overwrite a previously generated second set of condition codes.
Claim 2
Independent Claim
239 words
A method for comparing a first operand to a second operand comprising the steps of: EXCLUSIVE ORing the first operand and the second operand; subtracting the first operand from the second operand to provide a signed difference; generating a first set of condition codes comprising: ZERO (Z) if the first and second operands are logically identical CARRY (C) if the second operand is larger than the first operand; and SIGN (S) if the difference is positive; and logically combining the first set of condition codes to produce a second set of condition codes, whereby said second set of condition codes represents a logical truth value of the combination of each of a number of different logical predicates, said second set of condition codes comprising: Equal (EQ) if the first operand is equal to the second operand; Not Equal (NE) if the first operand is not equal to the second operand; Greater Than (GT) if the first operand is greater than the second operand; Greater than or Equal (GE) if the first operand is greater than the second operand; Less than or Equal (LE) if the first operand is less than or equal to the second operand; and providing the second set condition codes, as respective bits of a data operand, to any one of a predetermined number of data registers, whereby execution of a subsequent explicit evaluate instruction will not overwrite a previously generated second set of condition codes.
Claim 3
Dependent Claim
267 words
In a data processor having an execution unit capable of executing an explicit evaluate instruction: first means for EXCLUSIVE ORing a first operand and a second operand; second means for subtracting the first operand from the second operand to provide a signed difference; third means, coupled to said first and second means, for generating a first set of condition codes comprising: ZERO (Z) if the first and second operands are logically identical CARRY (C) if the second operand is larger than the first operand; and SIGN (S) if the difference is positive; and fourth means, coupled to said third means, for logically combining the first set of condition codes to produce a second set of condition codes, whereby said second set of condition codes represents a logical truth value of the combination of each of a number of different logical predicates, said second set of condition codes, comprising: Equal (EQ) if the first operand is equal to the second operand; Not Equal (NE) if the first operand is not equal to the second operand; Greater Than (GT) if the first operand is greater than the second operand; Greater than or Equal (GE) if the first operand is greater than the second operand; Less than or Equal (LE) if the first operand is less than or equal to the second operand; and fifth means for providing the second set of condition codes, as respective bits of a data operand, to any one of a predetermined number of data registers, whereby execution of a subsequent explicit evaluate instruction will not overwrite a previously generated second set of condition codes.
Claim 4
Dependent Claim
267 words
In a data processor having an execution unit capable of executing an explicit evaluate instruction: first means for EXCLUSIVE ORing a first operand and a second operand; second means for subtracting the first operand from the second operand to provide a signed difference; third means, coupled to said first and second means, for generating a first set of condition codes comprising: ZERO (Z) if the first and second operands are logically identical CARRY (C) if the second operand is larger than the first operand; and SIGN (S) if the difference is positive; and fourth means, coupled to said third means, for logically combining the first set of condition codes to produce a second set of condition codes, whereby said second set of condition codes represents a logical truth value of the combination of each of a number of different logical predicates, said second set of condition codes, comprising: Equal (EQ) if the first operand is equal to the second operand; Not Equal (NE) if the first operand is not equal to the second operand; Greater Than (GT) if the first operand is greater than the second operand; Greater than or Equal (GE) if the first operand is greater than the second operand; Less than or Equal (LE) if the first operand is less than or equal to the second operand; and fifth means for providing the second set of condition codes, as respective bits of a data operand, to any one of a predetermined number of data registers, whereby execution of a subsequent explicit evaluate instruction will not overwrite a previously generated second set of condition codes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-02 | 1993-10-02 | 1994-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-02 | 1997-10-02 | 1998-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-02 | 2001-10-02 | 2002-04-03 | $7700.00 | Window Closed / Lapsed |