US4920477A
Expired / Lapsed
US
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Virtual address table look aside buffer miss recovery method and apparatus
Assignee: Hewlett Packard Development Co LP
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Filing: 1987-04-20
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Granted: 1990-04-24
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Expires: 2007-04-20
Abstract
Abstract A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condition has been detected, the instruction causing the error condition, and those instructions entering the memory pipeline after the instruction causing the error condition, are replayed. The method and apparatus for replaying the instructions use first in-first out buffers for storing the virtual address data and instruction status data relating to each memory access instruction. That stored data is then retrieved after an error condition is detected so that the instruction sequence, beginning at the data miss, can be replayed.
Inventors
- 👤 Robert P. Colwell
- 👤 John O'Donnell
- 👤 David B. Papworth
- 👤 Paul K. Rodman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 04:17
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1063; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/1407
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
194 words
In a data processor having a central processing unit, and at least one pipelined memory controller circuitry responsive to the central processing unit and having a memory pipeline, said central processing unit addressing data using a virtual address memory table look aside buffer, miss recovery circuitry comprising a virtual address first in-first out buffer means for storing virtual address data from the central processing unit during at least each memory access instruction, an instruction status first in-first out buffer means for storing instruction status data generated in the memory circuitry during at least each memory access instruction, means for detecting a memory access error condition during execution of a memory access instruction in the memory circuitry, and a resequencing means having means responsive to detection of the memory access error condition for at least correcting said memory access error condition, and means for replaying, in sequence, after said error is corrected, the instruction causing the error condition and those instructions entering and in the memory pipeline after the instruction causing the error condition, said replaying means being responsive to the virtual address and instruction status first in-first out buffer means for replaying said instructions.
Claim 2
Dependent Claim
194 words
In a data processor having a central processing unit, and at least one pipelined memory controller circuitry responsive to the central processing unit and having a memory pipeline, said central processing unit addressing data using a virtual address memory table look aside buffer, miss recovery circuitry comprising a virtual address first in-first out buffer means for storing virtual address data from the central processing unit during at least each memory access instruction, an instruction status first in-first out buffer means for storing instruction status data generated in the memory circuitry during at least each memory access instruction, means for detecting a memory access error condition during execution of a memory access instruction in the memory circuitry, and a resequencing means having means responsive to detection of the memory access error condition for at least correcting said memory access error condition, and means for replaying, in sequence, after said error is corrected, the instruction causing the error condition and those instructions entering and in the memory pipeline after the instruction causing the error condition, said replaying means being responsive to the virtual address and instruction status first in-first out buffer means for replaying said instructions.
Claim 3
Dependent Claim
32 words
The apparatus of claim 1 wherein said instruction status data comprises at least: operation code data, status data identifying the type of error, and data representing the destination of the memory data.
Claim 4
Dependent Claim
25 words
The apparatus of claim 2 wherein said virtual address and instruction status first in-first out buffer means store solely data corresponding to memory access operations.
Claim 5
Dependent Claim
144 words
In a data processor having a central processing unit and at least one pipelined memory controller circuitry responsive to the central processing unit and having a memory pipeline, a virtual memory addressed table look aside buffer miss recovery method comprising the steps of storing sequentially generated virtual address data from the central processing unit in a virtual address first in-first out buffer, storing sequentially generated instruction status data in an instruction status first in-first out buffer, detecting a memory access error condition in memory controller access processing, correcting a memory access error causing said condition, and replaying, in sequence, the instruction causing the error condition and those instructions entering and in the memory pipeline after the instruction causing the error condition, said replaying step being responsive to data stored in said virtual address and instruction status first in-first out buffers for replaying said instructions.
Claim 6
Dependent Claim
144 words
In a data processor having a central processing unit and at least one pipelined memory controller circuitry responsive to the central processing unit and having a memory pipeline, a virtual memory addressed table look aside buffer miss recovery method comprising the steps of storing sequentially generated virtual address data from the central processing unit in a virtual address first in-first out buffer, storing sequentially generated instruction status data in an instruction status first in-first out buffer, detecting a memory access error condition in memory controller access processing, correcting a memory access error causing said condition, and replaying, in sequence, the instruction causing the error condition and those instructions entering and in the memory pipeline after the instruction causing the error condition, said replaying step being responsive to data stored in said virtual address and instruction status first in-first out buffers for replaying said instructions.
Claim 7
Dependent Claim
41 words
The method of claim 4 wherein said instruction status data storing step comprises the step of storing, in said instruction status buffer, operation code data, status data identifying the type of error, and data representing the destination of the memory data.
Claim 8
Dependent Claim
29 words
The method of claim 5 wherein said storing steps each comprise the step of loading said respective first in-first out buffer solely with data corresponding to memory access instructions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-23 | 1993-10-23 | 1994-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-23 | 1997-10-23 | 1998-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-23 | 2001-10-23 | 2002-04-24 | $7700.00 | Window Closed / Lapsed |