Patent US3935944A successfully refreshed from Google Patents.
Patent US4931354A successfully refreshed from Google Patents.
US4931354A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multilayer printed circuit board
Assignee: Murata Manufacturing Co Ltd
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Filing: 1988-11-01
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Granted: 1990-06-05
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Expires: 2008-11-01
Abstract
Abstract A multilayer printed circuit board comprises plural insulating layers integrated into one body, and internal wiring conductor layers located on the internal insulating layers, characterized in that conductor paths in each internal conductor layer are locally separated from the insulating layer by a cavity or porous layer provided at the boundaries between the path and insulating layer adjacent thereto. At least one insulating layer between internal conductor layers may be provided with a layered space or porous layer therein.
Inventors
- 👤 Kikuo Wakino
- 👤 Harufumi Mandai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:01
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0237; H05K1/024; H05K3/00; H05K3/46; H05K3/4697; H10W44/00; H10W44/601; H10W70/62; H10W70/63; H10W70/635; H05K1/03; H05K1/0306; H05K1/09; H05K1/092; H05K2201/00; H05K2201/01; H05K2201/0104; H05K2201/0116; H05K2203/00; H05K2203/30; H05K2203/308; H05K3/4611; H05K3/4626; H05K3/4629; Y; Y10; Y10S; Y10S428/00; Y10S428/901; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24917; Y10T428/24926
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
71 words
A multilayer printed circuit board comprising monolithic insulating layers and an internal wiring conductor layer located on a surface of at least one of said insulating layers and forming an internal conductor path, said conductor path in said internal conductor layer being locally separated from an adjacent insulating layer by a closed internal cavity located about said internal conductor path which reduces the dielectric constant of said multilayer printed circuit board.
Claim 2
Dependent Claim
71 words
A multilayer printed circuit board comprising monolithic insulating layers and an internal wiring conductor layer located on a surface of at least one of said insulating layers and forming an internal conductor path, said conductor path in said internal conductor layer being locally separated from an adjacent insulating layer by a closed internal cavity located about said internal conductor path which reduces the dielectric constant of said multilayer printed circuit board.
Claim 3
Dependent Claim
31 words
A multilayer printed circuit board claimed in claim 1 wherein said insulating layers are made up of a ceramic composition with a low sintering temperature of not more than 1000° C.
Claim 4
Dependent Claim
52 words
A multilayer printed circuit board claimed in claim 2 wherein said ceramic composition is a dielectric ceramic composition consisting essentially of 1 to 30% of Al 2 O 3 , 25 to 80% of SiO 2 , 15 to 70% of CaO, and 1.5 to 5% of B 2 O 3 .
Claim 5
Dependent Claim
42 words
A multilayer printed circuit board claimed in claim 1 wherein said conductor path in said internal conductor layer is separated from said adjacent insulating layer by a porous layer provided in said cavity between said adjacent insulating layer and said conductor layer.
Claim 6
Dependent Claim
105 words
A multilayer printed circuit board comprising monolithic insulating layers with at least one plated hole or through hole and an internal wire conductor layer located on a surface of at least two of said insulating layers and forming internal conductor paths interconnected by said plated hole or through hole; at least one of said internal insulating layers being positioned between said internal conductor layers and being formed with a closed internal layered space or porous layer extending substantially throughout the width of said internal insulating layer except for the area of said internal insulating layer in which the plated hole or through hole passes therethrough.
Claim 7
Dependent Claim
105 words
A multilayer printed circuit board comprising monolithic insulating layers with at least one plated hole or through hole and an internal wire conductor layer located on a surface of at least two of said insulating layers and forming internal conductor paths interconnected by said plated hole or through hole; at least one of said internal insulating layers being positioned between said internal conductor layers and being formed with a closed internal layered space or porous layer extending substantially throughout the width of said internal insulating layer except for the area of said internal insulating layer in which the plated hole or through hole passes therethrough.
Claim 8
Dependent Claim
113 words
A multilayer printed circuit board comprising: a plurality of monolithic insulating layers; an internal wiring conductor layer formed on a surface of at least one of said insulating layers; at least one plated through hole which passes through said board and conductively contacts said internal conductor layer; said internal wiring conductor layer being at least partially separated from an adjacent insulating layer by a closed internal region located about said internal conductor and containing means for reducing the dielectric constant of said multilayer printed circuit board; said means being selected from the group consisting of a cavity and a porous layer; and said closed internal region being spaced away from said through hole.
Claim 9
Dependent Claim
113 words
A multilayer printed circuit board comprising: a plurality of monolithic insulating layers; an internal wiring conductor layer formed on a surface of at least one of said insulating layers; at least one plated through hole which passes through said board and conductively contacts said internal conductor layer; said internal wiring conductor layer being at least partially separated from an adjacent insulating layer by a closed internal region located about said internal conductor and containing means for reducing the dielectric constant of said multilayer printed circuit board; said means being selected from the group consisting of a cavity and a porous layer; and said closed internal region being spaced away from said through hole.
References Cited (Backward Citations)
US4502939A
Cited
US4627160A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-04 | 1993-12-04 | 1994-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-04 | 1997-12-04 | 1998-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-04 | 2001-12-04 | 2002-06-05 | $7700.00 | Window Closed / Lapsed |