US4931992A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory having barrier transistors connected between sense and restore circuits
Assignee: Toshiba Corp
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Filing: 1989-02-09
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Granted: 1990-06-05
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Expires: 2009-02-09
Abstract
Abstract A semiconductor memory comprises a memory cell for storing data, a bit line pair for transfering the data, a sense amplifier for amplifying the data from the bit line pair, a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory, and a pair of constant voltage barrier transistors connected between the restore circuit and the sense amplifier for increasing the speed of sensing.
Inventors
- 👤 Masaki Ogihara
- 👤 Yoshio Okada
- 👤 Syuso Fujii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:20
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
106 words
A semiconductor memory operable in response to a power source potential Vcc, comprising: a memory cell for storing data; a bit line pair for transferring the data; a sense amplifier to amplifying the data from the bit line pair and for sensing the data stored in the memory cell; a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory; and barrier transistor means for increasing the speed of sensing, said barrier transistor means being connected between the sense amplifier and the restore circuit and having a gate and a constant gate potential sufficient to maintain an ON state.
Claim 2
Dependent Claim
106 words
A semiconductor memory operable in response to a power source potential Vcc, comprising: a memory cell for storing data; a bit line pair for transferring the data; a sense amplifier to amplifying the data from the bit line pair and for sensing the data stored in the memory cell; a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory; and barrier transistor means for increasing the speed of sensing, said barrier transistor means being connected between the sense amplifier and the restore circuit and having a gate and a constant gate potential sufficient to maintain an ON state.
Claim 3
Dependent Claim
28 words
The semiconductor memory according to claim 1, wherein the restore circuit comprises first and second MOS transistors forming a flipflop circuit controlled by a predetermined restore control signal.
Claim 4
Dependent Claim
37 words
The semiconductor memory according to claim 1 wherein the sense amplifier includes a plurality of MOS transistors of one conductivity type, and the barrier transistor means includes a plurality of barrier transistors of the same conductivity type.
Claim 5
Dependent Claim
31 words
The semiconductor memory according to claim 3 wherein the barrier transistors are N channel transistors and a Vcc power source potential is applied to the gates of the N channel transistors.
Claim 6
Dependent Claim
28 words
The semiconductor memory according to claim 3 wherein the barrier transistors are P channel transistors and earth potential is applied to the gates of the P channel transistors.
Claim 7
Dependent Claim
120 words
A semiconductor memory operable in response to a Vcc power source potential, comprising: a memory cell for storing data; a bit line pair for transferring the data; a precharge means for precharging the bit line pair to a potential of Vcc/2; a sense amplifier for amplifying the data from the bit line pair and for sensing the data stored in the memory cell; a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory; and barrier transistor means for increasing the speed of sensing, said barrier transistor means being connected between the sense amplifier and the restore circuit and having a gate and a fixed gate potential sufficient to maintain an ON state.
Claim 8
Dependent Claim
120 words
A semiconductor memory operable in response to a Vcc power source potential, comprising: a memory cell for storing data; a bit line pair for transferring the data; a precharge means for precharging the bit line pair to a potential of Vcc/2; a sense amplifier for amplifying the data from the bit line pair and for sensing the data stored in the memory cell; a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory; and barrier transistor means for increasing the speed of sensing, said barrier transistor means being connected between the sense amplifier and the restore circuit and having a gate and a fixed gate potential sufficient to maintain an ON state.
Claim 9
Dependent Claim
37 words
The semiconductor memory according to claim 6 wherein the sense amplifier includes a plurality of MOS transistors of one conductivity type, and the barrier transistor means includes a plurality of barrier transistors of the same conductivity type.
Claim 10
Dependent Claim
31 words
The semiconductor memory according to claim 7 wherein the barrier transistors are N channel transistors and a Vcc power source potential is applied to the gates of the N channel transistors.
Claim 11
Dependent Claim
28 words
The semiconductor memory according to claim 7 wherein the barrier transistors are P channel transistors and earth potential is applied to the gates of the P channel transistors.
Claim 12
Dependent Claim
121 words
A semiconductor memory operable in response to a power source potential Vcc, comprising: a memory cell for storing data; a bit line pair for transferring the data; a sense amplifier for amplifying the data from the bit line pair and for sensing the data stored in the memory cell; a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory; and barrier transistor means for increasing the speed of sensing and for transferring data from the sense amplifier to the bit line during a write operation, said barrier transistor means being connected between the sense amplifier and the restore circuit and having a gate and a gate potential sufficient to maintain an ON state.
Claim 13
Dependent Claim
121 words
A semiconductor memory operable in response to a power source potential Vcc, comprising: a memory cell for storing data; a bit line pair for transferring the data; a sense amplifier for amplifying the data from the bit line pair and for sensing the data stored in the memory cell; a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory; and barrier transistor means for increasing the speed of sensing and for transferring data from the sense amplifier to the bit line during a write operation, said barrier transistor means being connected between the sense amplifier and the restore circuit and having a gate and a gate potential sufficient to maintain an ON state.
Claim 14
Dependent Claim
136 words
A semiconductor memory operable in response to a power source potential Vcc, comprising: a memory cell for storing data; a bit line pair for transferring the data; a precharge means for precharging the bit line pair to a potential of substantially Vcc/2; a sense amplifier for amplifying the data from the bit line pair and for sensing the data stored in the memory cell; a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory; and barrier transistor means for increasing the speed of sensing and for transferring data from the sense amplifier to the bit line during a write operation, said barrier transistor means being connected between the sense amplifier and the restore circuit and having a gate and a gate potential sufficient to maintain an ON state.
Claim 15
Dependent Claim
136 words
A semiconductor memory operable in response to a power source potential Vcc, comprising: a memory cell for storing data; a bit line pair for transferring the data; a precharge means for precharging the bit line pair to a potential of substantially Vcc/2; a sense amplifier for amplifying the data from the bit line pair and for sensing the data stored in the memory cell; a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory; and barrier transistor means for increasing the speed of sensing and for transferring data from the sense amplifier to the bit line during a write operation, said barrier transistor means being connected between the sense amplifier and the restore circuit and having a gate and a gate potential sufficient to maintain an ON state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-04 | 1993-12-04 | 1994-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-04 | 1997-12-04 | 1998-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-04 | 2001-12-04 | 2002-06-05 | $7700.00 | Window Closed / Lapsed |