Patent US4937872A successfully refreshed from Google Patents.
US4937872A
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Neural computation by time concentration
Assignee: NCR Voyix Corp
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Filing: 1989-07-24
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Granted: 1990-06-26
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Expires: 2009-07-24
Abstract
Abstract Apparatus that solves the problem of pattern recognition in a temporal signal that is subject to distortions and time warp. The arrangement embodying the invention comprises a neural network, an input interconnection network, and a plurality of signal modification circuits. A plurality of input leads delivers a preselected characteristic stimulus to associated signal modification units, and in response to an applied stimulus, each signal modification unit develops a plurality of output signals that begins at the time of stimulus application, rises to a peak, and decays thereafter. The mean time delay of each output (time to reach the peak) is different for each of the modification unit output signals. The outputs of the signal modification units are applied to the input interconnection unit wherein connections are made in accordance with the sequences that are to be recognized.
Inventors
- 👤 John J. Hopfield
- 👤 David W. Tank
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:41
CPC Classifications
G; G10; G10L; G10L15/00; G10L15/08; G10L15/16; G10L25/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
82 words
A system for recognizing at least one pattern comprising: a plurality of stretchable delay means, each responsive to an applied input signal and each developing a set of different delayed signals, with said different delayed signals in each set differing from each other in delay and duration; an interconnection network for selectively connecting said delayed signals to a plurality of outputs; and a network responsive to said plurality of outputs for developing a preselected output signal indicative of recognition of said pattern.
Claim 2
Independent Claim
82 words
A system for recognizing at least one pattern comprising: a plurality of stretchable delay means, each responsive to an applied input signal and each developing a set of different delayed signals, with said different delayed signals in each set differing from each other in delay and duration; an interconnection network for selectively connecting said delayed signals to a plurality of outputs; and a network responsive to said plurality of outputs for developing a preselected output signal indicative of recognition of said pattern.
Claim 3
Dependent Claim
50 words
The system of claim 1 wherein each of said different delayed signals in said set are developed by transforming said applied input signal with a preselected function having a parameter other than one related to delay that is set to a different value for each of said different delayed signals.
Claim 4
Dependent Claim
24 words
The system of claim 1 wherein said input signal applied to each of said stretchable delay means corresponds to a component of said pattern.
Claim 5
Dependent Claim
36 words
The system of claim 1 wherein said selectively connecting in said interconnection network is achieved via conductances of a prechosen value that are connected between inputs of said interconnection network and outputs of said interconnection network.
Claim 6
Dependent Claim
46 words
The system of claim 1 further including pattern component detection means responsive to an input signal of the system for developing said input signal applied to each of said stretchable delay means corresponding to the detection of said pattern in said input signal of the system.
Claim 7
Dependent Claim
24 words
The system of claim 1 wherein said input signal applied to each of said stretchable delay means corresponds to different components of said pattern.
Claim 8
Dependent Claim
271 words
A pattern recognition system responsive to a input signal composed of concatenated pattern components, X m , and developing a plurality of output signals, V i , comprising: a feature detector responsive to said input signal for developing output signals D X .sbsb.m (t-τ), where m is a selected integer in the range 1 to M, M being an integer, developing and output signal that is 1 when pattern component X m is present within said input signal at time t=τ and 0 otherwise, τ being a selected constant, an M plurality of conditioners, each responsive to one of said D X .sbsb.m (t-τ) signals and developing K conditioner output signals, with each of said conditioner output signals being responsive to said D X .sbsb.m (t=τ) signal and to f k (τ), where k is an integer in the range 1 to K, K being another integer, and f k (τ) is a selected stretchable delay function that relates the k th output signal of a conditioner to the conditioner's input signal each of said f k (τ) functions being different from each other; and a decision circuit responsive to output signals of said conditioners that develops an output signal in accordance with an energy function describing the behavior of the circuit that decreases with time during operation of said decision circuit and includes the component ##EQU8## where T i X m ;k is a constant having a contributing value when X m with delay provided by f k (τ) contributes to the activation of said signal V i as part of said pattern recognition, and having a noncontributing value otherwise.
Claim 9
Dependent Claim
271 words
A pattern recognition system responsive to a input signal composed of concatenated pattern components, X m , and developing a plurality of output signals, V i , comprising: a feature detector responsive to said input signal for developing output signals D X .sbsb.m (t-τ), where m is a selected integer in the range 1 to M, M being an integer, developing and output signal that is 1 when pattern component X m is present within said input signal at time t=τ and 0 otherwise, τ being a selected constant, an M plurality of conditioners, each responsive to one of said D X .sbsb.m (t-τ) signals and developing K conditioner output signals, with each of said conditioner output signals being responsive to said D X .sbsb.m (t=τ) signal and to f k (τ), where k is an integer in the range 1 to K, K being another integer, and f k (τ) is a selected stretchable delay function that relates the k th output signal of a conditioner to the conditioner's input signal each of said f k (τ) functions being different from each other; and a decision circuit responsive to output signals of said conditioners that develops an output signal in accordance with an energy function describing the behavior of the circuit that decreases with time during operation of said decision circuit and includes the component ##EQU8## where T i X m ;k is a constant having a contributing value when X m with delay provided by f k (τ) contributes to the activation of said signal V i as part of said pattern recognition, and having a noncontributing value otherwise.
Claim 10
Dependent Claim
18 words
The system of claim 7 wherein said contributing value is a 1 and said noncontributing value is 0.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-06-25 | 1993-12-25 | 1994-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-25 | 1997-12-25 | 1998-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-25 | 2001-12-25 | 2002-06-26 | $7700.00 | Window Closed / Lapsed |