Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a plurality of memory arrays; array selection means for receiving a predetermined address signal and for selectively generating an array selection signal to select a predetermined one of said memory arrays; row and column address decoders disposed in such a manner as to respectively correspond to said memory arrays; a plurality of amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selecting means for generating a signal to selectively operate, in accordance with said array selection signal, a predetermined one of said row address decoders corresponding to said selected memory array, a predetermined one of said column address decoders corresponding to said selected memory array, and a predetermined one of said amplifiers corresponding to said selected memory array.

Claim 3

A semiconductor memory device according to claim 1, wherein said semiconductor memory device is a dynamic RAM and wherein said amplifiers include sense amplifiers and main amplifiers disposed in such a manner as to correspond to said memory arrays and operated selectively in accordance with said array selection signal.

Claim 4

A semiconductor memory device according to claim 1, wherein said address signal is part of row address signals.

Claim 5

A semiconductor memory device comprising: a plurality of memory arrays, each including a plurality of memory cells disposed in matrix; a plurality of external terminals for address signals; first and second control external terminals; address signal generation means connected to said external terminals for address signals and to said first and second external terminals, for generating row address signals in accordance with address signals at said external terminals for said address signals in synchronism with a first strobe signal supplied thereto through said first control external terminal, and for generating column address signals in accordance with address signals at said external terminals for said address signals in synchronism with a second strobe signal supplied thereto through said second control external terminal; a plurality of row address decoders disposed in such a manner as to correspond to said memory arrays, respectively, for selecting a plurality of memory cells designated by predetermined row address signals among said row address signals from said memory array corresponding thereto; a plurality of column address decoders disposed in such a manner as to correspond to said memory arrays, respectively, for selecting a plurality of memory cells designated by said column address signals from said memory array corresponding thereto; a plurality of main amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selection signal generation means for generating a selection signal for operating a predetermined row address decoder among said row address decoders, a predetermined column address decoder among said column address decoders and a predetermined main amplifier among said main amplifiers upon receiving at least part of row address signals among said row address signals.

Claim 6

A semiconductor memory device comprising: a plurality of memory arrays, each including a plurality of memory cells disposed in matrix; a plurality of external terminals for address signals; first and second control external terminals; address signal generation means connected to said external terminals for address signals and to said first and second external terminals, for generating row address signals in accordance with address signals at said external terminals for said address signals in synchronism with a first strobe signal supplied thereto through said first control external terminal, and for generating column address signals in accordance with address signals at said external terminals for said address signals in synchronism with a second strobe signal supplied thereto through said second control external terminal; a plurality of row address decoders disposed in such a manner as to correspond to said memory arrays, respectively, for selecting a plurality of memory cells designated by predetermined row address signals among said row address signals from said memory array corresponding thereto; a plurality of column address decoders disposed in such a manner as to correspond to said memory arrays, respectively, for selecting a plurality of memory cells designated by said column address signals from said memory array corresponding thereto; a plurality of main amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selection signal generation means for generating a selection signal for operating a predetermined row address decoder among said row address decoders, a predetermined column address decoder among said column address decoders and a predetermined main amplifier among said main amplifiers upon receiving at least part of row address signals among said row address signals.

Claim 7

A semiconductor memory device according to claim 4, wherein each of said memory cells includes a storage capacitor and a switch device for selecting the address.

Claim 8

A semiconductor memory device according to claim 5, wherein the same selection signal is supplied from said selection signal generation means to said row address decoder and said column address decoder that are to be operated.

Claim 9

A semiconductor memory device according to claim 6, wherein each of said column address decoder and said row address decoder includes a decoder circuit to which a power source voltage is selectively supplied in accordance with a selection signal supplied thereto.

Claim 10

A semiconductor memory device according to claim 6, wherein each of said column address decoders selects a plurality of memory cells from at least two memory arrays.

Claim 11

A semiconductor memory device according to claim 8, wherein said row address decoder is disposed in such a manner as to correspond to said memory array on the 1:1 basis.

Claim 12

A semiconductor memory device comprising: a plurality of memory arrays; array selection means for receiving a predetermined address signal and for selectively generating an array selection signal to select a predetermined one of said memory arrays; row and column address decoders disposed in such a manner as to respectively correspond to said memory arrays; a plurality of amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selecting means for generating a signal to selectively operate, in accordance with said array selection signal, a predetermined one of said row address decoders corresponding to said selected memory array, a predetermined one of said column address decoders corresponding to said selected memory array, and a predetermined one of said amplifiers corresponding to said selected memory array so that only said predetermined row address decoder, said predetermined column address decoder and said predetermined amplifier are operated while row address decoders, column address decoders and amplifiers corresponding to non-selected memory arrays are not operated.

Claim 13

A semiconductor memory device comprising: a plurality of memory arrays; array selection means for receiving a predetermined address signal and for selectively generating an array selection signal to select a predetermined one of said memory arrays; row and column address decoders disposed in such a manner as to respectively correspond to said memory arrays; a plurality of amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selecting means for generating a signal to selectively operate, in accordance with said array selection signal, a predetermined one of said row address decoders corresponding to said selected memory array, a predetermined one of said column address decoders corresponding to said selected memory array, and a predetermined one of said amplifiers corresponding to said selected memory array so that only said predetermined row address decoder, said predetermined column address decoder and said predetermined amplifier are operated while row address decoders, column address decoders and amplifiers corresponding to non-selected memory arrays are not operated.

Claim 14

A semiconductor memory device according to claim 10, wherein said semiconductor memory device is a dynamic RAM and wherein said amplifiers include sense amplifiers and main amplifiers disposed in such a manner as to correspond to said memory arrays and operated selectively in accordance with said array selection signal.

Claim 15

A semiconductor memory device according to claim 10, wherein said address signal is part of row address signals.