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US4941129A
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1988-08-29
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Granted: 1990-07-10
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Expires: 2008-08-29
Abstract
Abstract A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.
Inventors
- 👤 Kazuyoshi Oshima
- 👤 Takashi Yamazaki
- 👤 Yasuhiro Kasama
- 👤 Tetsu Udagawa
- 👤 Hiroaki Kotani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C8/00; G11C8/12; G11C11/401; G11C11/4063; G11C11/407
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
129 words
A semiconductor memory device comprising: a plurality of memory arrays; array selection means for receiving a predetermined address signal and for selectively generating an array selection signal to select a predetermined one of said memory arrays; row and column address decoders disposed in such a manner as to respectively correspond to said memory arrays; a plurality of amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selecting means for generating a signal to selectively operate, in accordance with said array selection signal, a predetermined one of said row address decoders corresponding to said selected memory array, a predetermined one of said column address decoders corresponding to said selected memory array, and a predetermined one of said amplifiers corresponding to said selected memory array.
Claim 2
Dependent Claim
129 words
A semiconductor memory device comprising: a plurality of memory arrays; array selection means for receiving a predetermined address signal and for selectively generating an array selection signal to select a predetermined one of said memory arrays; row and column address decoders disposed in such a manner as to respectively correspond to said memory arrays; a plurality of amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selecting means for generating a signal to selectively operate, in accordance with said array selection signal, a predetermined one of said row address decoders corresponding to said selected memory array, a predetermined one of said column address decoders corresponding to said selected memory array, and a predetermined one of said amplifiers corresponding to said selected memory array.
Claim 3
Dependent Claim
49 words
A semiconductor memory device according to claim 1, wherein said semiconductor memory device is a dynamic RAM and wherein said amplifiers include sense amplifiers and main amplifiers disposed in such a manner as to correspond to said memory arrays and operated selectively in accordance with said array selection signal.
Claim 4
Dependent Claim
18 words
A semiconductor memory device according to claim 1, wherein said address signal is part of row address signals.
Claim 5
Dependent Claim
275 words
A semiconductor memory device comprising: a plurality of memory arrays, each including a plurality of memory cells disposed in matrix; a plurality of external terminals for address signals; first and second control external terminals; address signal generation means connected to said external terminals for address signals and to said first and second external terminals, for generating row address signals in accordance with address signals at said external terminals for said address signals in synchronism with a first strobe signal supplied thereto through said first control external terminal, and for generating column address signals in accordance with address signals at said external terminals for said address signals in synchronism with a second strobe signal supplied thereto through said second control external terminal; a plurality of row address decoders disposed in such a manner as to correspond to said memory arrays, respectively, for selecting a plurality of memory cells designated by predetermined row address signals among said row address signals from said memory array corresponding thereto; a plurality of column address decoders disposed in such a manner as to correspond to said memory arrays, respectively, for selecting a plurality of memory cells designated by said column address signals from said memory array corresponding thereto; a plurality of main amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selection signal generation means for generating a selection signal for operating a predetermined row address decoder among said row address decoders, a predetermined column address decoder among said column address decoders and a predetermined main amplifier among said main amplifiers upon receiving at least part of row address signals among said row address signals.
Claim 6
Dependent Claim
275 words
A semiconductor memory device comprising: a plurality of memory arrays, each including a plurality of memory cells disposed in matrix; a plurality of external terminals for address signals; first and second control external terminals; address signal generation means connected to said external terminals for address signals and to said first and second external terminals, for generating row address signals in accordance with address signals at said external terminals for said address signals in synchronism with a first strobe signal supplied thereto through said first control external terminal, and for generating column address signals in accordance with address signals at said external terminals for said address signals in synchronism with a second strobe signal supplied thereto through said second control external terminal; a plurality of row address decoders disposed in such a manner as to correspond to said memory arrays, respectively, for selecting a plurality of memory cells designated by predetermined row address signals among said row address signals from said memory array corresponding thereto; a plurality of column address decoders disposed in such a manner as to correspond to said memory arrays, respectively, for selecting a plurality of memory cells designated by said column address signals from said memory array corresponding thereto; a plurality of main amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selection signal generation means for generating a selection signal for operating a predetermined row address decoder among said row address decoders, a predetermined column address decoder among said column address decoders and a predetermined main amplifier among said main amplifiers upon receiving at least part of row address signals among said row address signals.
Claim 7
Dependent Claim
26 words
A semiconductor memory device according to claim 4, wherein each of said memory cells includes a storage capacitor and a switch device for selecting the address.
Claim 8
Dependent Claim
36 words
A semiconductor memory device according to claim 5, wherein the same selection signal is supplied from said selection signal generation means to said row address decoder and said column address decoder that are to be operated.
Claim 9
Dependent Claim
41 words
A semiconductor memory device according to claim 6, wherein each of said column address decoder and said row address decoder includes a decoder circuit to which a power source voltage is selectively supplied in accordance with a selection signal supplied thereto.
Claim 10
Dependent Claim
27 words
A semiconductor memory device according to claim 6, wherein each of said column address decoders selects a plurality of memory cells from at least two memory arrays.
Claim 11
Dependent Claim
30 words
A semiconductor memory device according to claim 8, wherein said row address decoder is disposed in such a manner as to correspond to said memory array on the 1:1 basis.
Claim 12
Dependent Claim
165 words
A semiconductor memory device comprising: a plurality of memory arrays; array selection means for receiving a predetermined address signal and for selectively generating an array selection signal to select a predetermined one of said memory arrays; row and column address decoders disposed in such a manner as to respectively correspond to said memory arrays; a plurality of amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selecting means for generating a signal to selectively operate, in accordance with said array selection signal, a predetermined one of said row address decoders corresponding to said selected memory array, a predetermined one of said column address decoders corresponding to said selected memory array, and a predetermined one of said amplifiers corresponding to said selected memory array so that only said predetermined row address decoder, said predetermined column address decoder and said predetermined amplifier are operated while row address decoders, column address decoders and amplifiers corresponding to non-selected memory arrays are not operated.
Claim 13
Dependent Claim
165 words
A semiconductor memory device comprising: a plurality of memory arrays; array selection means for receiving a predetermined address signal and for selectively generating an array selection signal to select a predetermined one of said memory arrays; row and column address decoders disposed in such a manner as to respectively correspond to said memory arrays; a plurality of amplifiers disposed in such a manner as to respectively correspond to said memory arrays; and selecting means for generating a signal to selectively operate, in accordance with said array selection signal, a predetermined one of said row address decoders corresponding to said selected memory array, a predetermined one of said column address decoders corresponding to said selected memory array, and a predetermined one of said amplifiers corresponding to said selected memory array so that only said predetermined row address decoder, said predetermined column address decoder and said predetermined amplifier are operated while row address decoders, column address decoders and amplifiers corresponding to non-selected memory arrays are not operated.
Claim 14
Dependent Claim
49 words
A semiconductor memory device according to claim 10, wherein said semiconductor memory device is a dynamic RAM and wherein said amplifiers include sense amplifiers and main amplifiers disposed in such a manner as to correspond to said memory arrays and operated selectively in accordance with said array selection signal.
Claim 15
Dependent Claim
18 words
A semiconductor memory device according to claim 10, wherein said address signal is part of row address signals.
References Cited (Backward Citations)
US4658377A
Cited
US4758993A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-09 | 1994-01-08 | 1994-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-09 | 1998-01-08 | 1998-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-09 | 2002-01-08 | 2002-07-10 | $7700.00 | Window Closed / Lapsed |