Patent US4954877A successfully refreshed from Google Patents.
US4954877A
Expired / Lapsed
US
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Chip carrier
Assignee: Hitachi Ltd
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Filing: 1989-08-02
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Granted: 1990-09-04
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Expires: 2009-08-02
Abstract
Abstract The present invention relates to a chip carrier, on which LSI chips are mounted and a chip carrier is disclosed, in which a region where power source throughholes are arranged and a region where signal throughholes are arranged are separated from each other and a coupling capacitor is formed only in the region where the power source throughholes are arranged with an intention to reduce noise.
Inventors
- 👤 Keiichirou Nakanishi
- 👤 Minoru Yamada
- 👤 Masakazu Yamamoto
- 👤 Satoru Ogihara
- 👤 Hiroichi Shinohara
- 👤 Hideo Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:31
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/601; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/851; H10W72/874; H10W72/877; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
75 words
A chip carrier comprising: a subboard; at least one LSI chip disposed on said subboard; signal through-holes disposed only on a first region of said subboard for inputting/outputting signals in/from said chip; power through-holes disposed only on a second region of said subboard for supplying electric power to said chip; and high dielectric constant material disposed on said second region and having a specific dielectric constant higher than that of the material constituting said subboard.
Claim 2
Dependent Claim
75 words
A chip carrier comprising: a subboard; at least one LSI chip disposed on said subboard; signal through-holes disposed only on a first region of said subboard for inputting/outputting signals in/from said chip; power through-holes disposed only on a second region of said subboard for supplying electric power to said chip; and high dielectric constant material disposed on said second region and having a specific dielectric constant higher than that of the material constituting said subboard.
Claim 3
Dependent Claim
27 words
A chip carrier according to claim 1, wherein said high dielectric constant material is sheet-shaped and buried in said subboard so as to cover said second region.
Claim 4
Dependent Claim
67 words
A chip carrier according to claim 2, wherein a first surface of said sheet-shaped high dielectric constant material is electrically in contact with an electrode connected with a through-hole at a power source potential among said power through-holes and a second surface of said sheet-shaped high dielectric constant material is electrically in contact with an electrode connected with a through-hole at ground potential among said power through-holes.
Claim 5
Dependent Claim
29 words
A chip carrier according to claim 1, wherein said first region is a peripheral portion of said subboard and said second region is the central portion of said subboard.
Claim 6
Dependent Claim
56 words
A chip carrier according to claim 4, wherein said high dielectric constant material is sheet-shaped, which covers said second region of said subboard and a part of which traverses a part of said first region so as to be in contact with guide pins for positioning said high dielectric constant material disposed outside of said subboard.
Claim 7
Dependent Claim
44 words
A chip carrier according to claim 4, wherein said sheet-shaped high dielectric constant material is buried in a sheet having a dielectric constant lower than that of said high dielectric constant material and disposed within said subboard so as to cover said second region.
Claim 8
Dependent Claim
29 words
A chip carrier according to claim 1, wherein said first region is the central portion of said subboard and said second region is a peripheral portion of said subboard.
Claim 9
Dependent Claim
27 words
A chip carrier according to claim 1, wherein said high dielectric constant material is far from a center of said signal through-holes at least by 100 μm.
Claim 10
Dependent Claim
20 words
A chip carrier according to claim 1, wherein said high dielectric constant material is disposed only on said second region.
Claim 11
Dependent Claim
91 words
A chip carrier comprising: a board; LSI chips disposed on said board; a plurality of signal through-holes traversing said board and transmitting signals to said chips; a plurality of power through-holes traversing said board and supplying electric power to said chips; and capacitor forming members comprising a capacitor disposed between a through-hole at a power source potential and a through-hole at ground potential among said power through-holes; wherein the distance between said capacitor forming members and a center of the signal through-hole, closest thereto is at least equal to 100 μm.
Claim 12
Dependent Claim
91 words
A chip carrier comprising: a board; LSI chips disposed on said board; a plurality of signal through-holes traversing said board and transmitting signals to said chips; a plurality of power through-holes traversing said board and supplying electric power to said chips; and capacitor forming members comprising a capacitor disposed between a through-hole at a power source potential and a through-hole at ground potential among said power through-holes; wherein the distance between said capacitor forming members and a center of the signal through-hole, closest thereto is at least equal to 100 μm.
Claim 13
Dependent Claim
106 words
A chip carrier comprising: a board; a plurality of terminals disposed on the lower surface of said board; signal through-holes and power through-holes connected with said plurality of terminals and disposed within said board; and LSI chips disposed on said board, signals being in/outputted in/from said LSI chips through said signal through-holes, electric power being supplied thereto through said power through-holes; wherein a region where said power through-holes are arranged and a region where said signal through-holes are arranged are separated from each other and a coupling capacitor is provided between a power through-hole at a power source potential and a power through-hole at ground potential.
Claim 14
Dependent Claim
106 words
A chip carrier comprising: a board; a plurality of terminals disposed on the lower surface of said board; signal through-holes and power through-holes connected with said plurality of terminals and disposed within said board; and LSI chips disposed on said board, signals being in/outputted in/from said LSI chips through said signal through-holes, electric power being supplied thereto through said power through-holes; wherein a region where said power through-holes are arranged and a region where said signal through-holes are arranged are separated from each other and a coupling capacitor is provided between a power through-hole at a power source potential and a power through-hole at ground potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |