Process for simultaneously fabricating EEPROM cell and flash EPROM cell

Claim 2

In a process for fabricating a first erasable electrical programmable read-only memory cell on a substrate, an improvement for simultaneously forming a second electrically erasable read-only memory cell on said substrate comprising the steps of: forming a first insulative region on said substrate for said first cell while simultaneously forming a second insulative region on said substrate, said second insulative region being utilized for the tunneling of charge in said second cell; forming a narrow polysilicon member from a layer of polysilicon deposited over said second insulative region while simultaneously forming polysilicon gates from said polysilicon layer for said first cell; doping said substrate adjacent to said narrow polysilicon member with a first dopant while simultaneously forming source and drain regions with said first dopant for said first cell; driving said first dopant under said narrow polysilicon member to form doped regions said doped regions being spaced-apart so as to define a narrow channel region therebetween such that electrical charge may be tunneled to and from said member through said doped regions.

Claim 3

The improvement defined by claim 1 wherein said doping is done in alignment with said polysilicon member.

Claim 4

The improvement defined by claim 2 including a second doping step wherein said source region of said first cell in said substrate adjacent to said narrow polysilicon member are doped with a second dopant.

Claim 5

The improvement defined by claim 3 wherein said second dopant comprises phosphorus.

Claim 6

In a process for fabricating a first erasable electrically programmable read-only memory cell on a substrate, an improvement for simultaneously forming a second electrically erasable and electrically programmable read-only memory cell on said substrate comprising the steps of: forming a second insulative region on said substrate for the tunneling of charge in said second cell simultaneously with the formation of a first insulative region on said substrate for said first cell; forming a narrow polysilicon member from a first layer of polysilicon deposited on said first and second insulative regions, said first layer forming a floating gate for said second cell, said polysilicon member extending from said floating gate of said second cell over said second insulative region, said first layer also forming a polysilicon gate for said first cell; doping said substrate adjacent to said polysilicon member with a first dopant while simultaneously forming source and drain regions with said first dopant for said first cell; driving said first dopant under said narrow polysilicon member to form at least one doped region under said member such that electrical charge may be tunneled to and from said floating gate of second cell through said second insulative region.

Claim 7

In a process for fabricating a first erasable electrically programmable read-only memory cell on a substrate, an improvement for simultaneously forming a second electrically erasable and electrically programmable read-only memory cell on said substrate comprising the steps of: forming a second insulative region on said substrate for the tunneling of charge in said second cell simultaneously with the formation of a first insulative region on said substrate for said first cell; forming a narrow polysilicon member from a first layer of polysilicon deposited on said first and second insulative regions, said first layer forming a floating gate for said second cell, said polysilicon member extending from said floating gate of said second cell over said second insulative region, said first layer also forming a polysilicon gate for said first cell; doping said substrate adjacent to said polysilicon member with a first dopant while simultaneously forming source and drain regions with said first dopant for said first cell; driving said first dopant under said narrow polysilicon member to form at least one doped region under said member such that electrical charge may be tunneled to and from said floating gate of second cell through said second insulative region.

Claim 8

The improvement defined by claim 5 wherein said doping is done in alignment with said polysilicon member.

Claim 9

The improvement defined by claim 6 including a second doping step wherein said source region of said first cell and said substrate adjacent to said narrow polysilicon member are doped with a second dopant.

Claim 10

The improvement defined by claim 7 wherein said second dopant comprises phosphorus.

Claim 11

In the fabrication of a flash EPROM on a substrate simultaneously with an EPROM, said flash EPROM including a floating gate and a control gate, said floating gate including a finger which extends over a tunnel oxide region, said floating gate finger and said tunnel oxide comprising said EEPROM, an improvement in the processing for forming said EEPROM comprising the steps of: doping said substrate with a first dopant in alignment with said floating gate finger after said floating gate finger has been formed over said tunnel oxide region; driving said dopant under said floating gate finger, thereby forming a pair of spaced-apart doped regions for facilitating the transfer of electrical charge to and from said floating gate finger.

Claim 12

In the fabrication of a flash EPROM on a substrate simultaneously with an EPROM, said flash EPROM including a floating gate and a control gate, said floating gate including a finger which extends over a tunnel oxide region, said floating gate finger and said tunnel oxide comprising said EEPROM, an improvement in the processing for forming said EEPROM comprising the steps of: doping said substrate with a first dopant in alignment with said floating gate finger after said floating gate finger has been formed over said tunnel oxide region; driving said dopant under said floating gate finger, thereby forming a pair of spaced-apart doped regions for facilitating the transfer of electrical charge to and from said floating gate finger.

Claim 13

Improvement defined by claim 9 wherein at least one of said pair of spaced-apart doped regions is contiguous with the drain region of said cell.

Claim 14

In the fabrication of a first electrically erasable programmable read-only memory cell on a substrate simultaneously with a second electrically programmable and electrically erasable memory cell formed on said substrate where said second cell has a floating gate finger disposed over a thin oxide region from which charge is tunneled through said oxide region into a doped region formed in said substrate under a portion of said floating gate finger, improved processing for forming said doped region comprising the steps of: doping said substrate adjacent to said floating gate finger of said second cell with at least one dopant; driving the dopant under said floating gate finger thereby forming a pair of spaced-apart doped regions for facilitating the tunnelling of said charge.

Claim 15

In the fabrication of a first electrically erasable programmable read-only memory cell on a substrate simultaneously with a second electrically programmable and electrically erasable memory cell formed on said substrate where said second cell has a floating gate finger disposed over a thin oxide region from which charge is tunneled through said oxide region into a doped region formed in said substrate under a portion of said floating gate finger, improved processing for forming said doped region comprising the steps of: doping said substrate adjacent to said floating gate finger of said second cell with at least one dopant; driving the dopant under said floating gate finger thereby forming a pair of spaced-apart doped regions for facilitating the tunnelling of said charge.

Claim 16

The processing defined by claim 11 wherein said doping step comprises two ion implantation steps.

Claim 17

The processing defined by claim 12 wherein arsenic and phosphorus are used as the dopants in said ion implantation steps.