Computer with interface for fast and slow memory circuits

Claim 2

A computer which provides a video signal for a display comprising: a central processing unit (CPU) which executes a program to provide said video signal for said display; first and second random-access memories (RAMs) couples to said CPU, both of said memories storing video data, and said CPU accessing said first RAM at a first rate and said second RAM at a second rate, said second rate being faster than said first rate; video circuits coupled to said first and second RAM, and to said display for generating said video signal from said video data stored in said first RAM for said display, said circuits accessing said first RAM at said first rate, said video data being updated and stored in both said first RAM and said second RAM; an interface means for providing control between said CPU and said first and second RAMs such that when said CPU is executing said program and needs to read said video data, said interface means causes said video data to read only said second RAM by said CPU thereby allowing said CPU to operate a substantial portion of its time at said second rate.

Claim 3

The computer defined by claim 1 including at least one first connector and at least one second connector, said first and second connectors being coupled to said CPU, said interface means for permitting data to be accessed at said first connector at said first rate and at said second connector at said second rate.

Claim 4

The computer defined by claim 2 including a read-only memory (ROM) coupled to said CPU and said interface means, said interface means causing said ROM to be accessed by said CPU at said second rate.

Claim 5

The computer defined by claim 3 wherin said interface means includes a decoder which decodes addresses from said CPU and from said addresses provides said control at one of said first and second rates.

Claim 6

The computer defined in claims 1 or 4 wherein said computer includes a data bus and an address bus, said CPU providing certain address signals on said data bus during predetermined periods.

Claim 7

The computer defined by claim 5 wherein said interface means includes a plurality of registers coupled to said data bus for receiving said certain addresses.

Claim 8

A computer which provides a video signal for a display comprising: a central processing unit (CPU); a data bus coupled to said CPU; an address bus coupled to said CPU; a first random-access memory (RAM) coupled to said data bus and said address bus; a second RAM coupled to said data bus said address bus, said first and second RAMs storing video data, said video data written by said CPU into said second RAM and then into said first RAM during a shadow cycle, said CPU accessing said first RAM at a first rate and said second RAM at a second rate, said second rate being faster than said first rate; video circuits coupled to said first and second RAM, and to said display for generating said video signal from said video data stored in said first RAM for said display, said circuit accessing said first RAM at said first rate, said video data being updated and stored in both said first RAM and said second RAM; an interface means coupled to said data bus, said address bus, said first RAM and said second RAM, for controlling first memory cycles between said CPU and said first RAM at said first and second memory cycles between said CPU and said second RAM at said second rate; said interface means including decoding means for decoding addresses from said CPU to select between said first and said second memory cycles such that when said CPU is executing a program and needs to update said video data, said interface means causes sia video data to be read only from said second RAM by said CPU thereby allowing said CPU to operate a substantial portion of its time at said second rate; said interface means also including timing means for synchronizing cetain memory cells with said first RAM.

Claim 9

A computer which provides a video signal for a display comprising: a central processing unit (CPU); a data bus coupled to said CPU; an address bus coupled to said CPU; a first random-access memory (RAM) coupled to said data bus and said address bus; a second RAM coupled to said data bus said address bus, said first and second RAMs storing video data, said video data written by said CPU into said second RAM and then into said first RAM during a shadow cycle, said CPU accessing said first RAM at a first rate and said second RAM at a second rate, said second rate being faster than said first rate; video circuits coupled to said first and second RAM, and to said display for generating said video signal from said video data stored in said first RAM for said display, said circuit accessing said first RAM at said first rate, said video data being updated and stored in both said first RAM and said second RAM; an interface means coupled to said data bus, said address bus, said first RAM and said second RAM, for controlling first memory cycles between said CPU and said first RAM at said first and second memory cycles between said CPU and said second RAM at said second rate; said interface means including decoding means for decoding addresses from said CPU to select between said first and said second memory cycles such that when said CPU is executing a program and needs to update said video data, said interface means causes sia video data to be read only from said second RAM by said CPU thereby allowing said CPU to operate a substantial portion of its time at said second rate; said interface means also including timing means for synchronizing cetain memory cells with said first RAM.

Claim 10

The computer defined by claim 7 wherein said first and second RAM are fabricated from the same dynamic access memory ports.

Claim 11

The computer defined by claim 7 wherein said video circuits include a video graphics controller which provides a timing signal to said timing means of said interface means.

Claim 12

The computer defined by claim 9 wherein said video circuits periodically have an extended cycle and wherein the occurrence of said extended cycle triggers said timing signal.

Claim 13

A computer which provides a video signal for a display comprising: a central processing unit (CPU) which executes a program; a data bus coupled to said CPU; an address bus coupled to said CPU; a first random-access memory (RAM) coupled to said data bus and said address bus; a second RAM coupled to said data bus and said address bus, said first and said second RAMs both storing the same video data, said video data being written by said CPU into said second RAM and then into said first RAM during a shadow cycle, said CPU accessing first RAM at a first rate and said second RAM at a second rate, said second rate being faster than said first rate; video circuits coupled to said first and second RAM, and to said display for generating said video signal from said video data stored in said first RAM for said display, said circuits accessing said first RAM at said first rate which is compatible with the video timing requirements of said computer, said video data being updated and stored in both said first RAM and said second RAM; an interface means coupled to said data bus, said address bus, said first RAM and said second RAM, for controlling first memory cycles between said CPU and said first RAM at said first rate, and second memory cycles between said CPU and said second RAM at a second rate, said first rate being slower than said second rate; said interface means including decoding means for decoding addresses from said CPU to select between said first and second memory cycles, and registers coupled to said decoding means and said bus for receiving certain address signals from said data bus during predetermined periods such that when said CPU is executing said program and needs to update said video data, said interface means causes said video data to be read only from said second RAM by said CPU thereby saving substantial time during updating of said display and allowing said CPU to operate a substantial portion of its time at said second rate, updated video data being written into said first and second RAMs by said CPU

Claim 14

A computer which provides a video signal for a display comprising: a central processing unit (CPU) which executes a program; a data bus coupled to said CPU; an address bus coupled to said CPU; a first random-access memory (RAM) coupled to said data bus and said address bus; a second RAM coupled to said data bus and said address bus, said first and said second RAMs both storing the same video data, said video data being written by said CPU into said second RAM and then into said first RAM during a shadow cycle, said CPU accessing first RAM at a first rate and said second RAM at a second rate, said second rate being faster than said first rate; video circuits coupled to said first and second RAM, and to said display for generating said video signal from said video data stored in said first RAM for said display, said circuits accessing said first RAM at said first rate which is compatible with the video timing requirements of said computer, said video data being updated and stored in both said first RAM and said second RAM; an interface means coupled to said data bus, said address bus, said first RAM and said second RAM, for controlling first memory cycles between said CPU and said first RAM at said first rate, and second memory cycles between said CPU and said second RAM at a second rate, said first rate being slower than said second rate; said interface means including decoding means for decoding addresses from said CPU to select between said first and second memory cycles, and registers coupled to said decoding means and said bus for receiving certain address signals from said data bus during predetermined periods such that when said CPU is executing said program and needs to update said video data, said interface means causes said video data to be read only from said second RAM by said CPU thereby saving substantial time during updating of said display and allowing said CPU to operate a substantial portion of its time at said second rate, updated video data being written into said first and second RAMs by said CPU

Claim 15

The computer defined by claim 11 wherein a first of said registers receives signals representing locations in said first RAM into which digital signals representing a video display are written.

Claim 16

The computer defined by claim 11 wherein a second of said registers receives part of a direct memory access address.

Claim 17

The computer defined by claim 11 wherein said computer includes a plurality of slots for receiving additional circuits and a third of said registers receives signals directing access to said slots.

Claim 18

A computer comprising a central processing unit CPU); a first random-access memory (RAM) coupled to said CPU; a second random-access memory (RAM) coupled to said CPU, said first and said second RAMs both storing the same video data, second RAM being accessed at a faster rate as compared to said second RAM; video circuits for providing video signals for a video display, said video signals being developed from said video data stored in said second RAM, said second RAM being coupled to said video circuits; CPU interface means for providing control between said CPU and said first and second RAMs, said interface means providing a control signal to said CPU and said first and second RAMs to selectively control access of said CPU to said RAMs such that when said control signal is in one state said video circuitry reads said second RAM to provide said video signal to said display, and when said control signal is in another state said CPU reads said first RAM to update said video data, said CPU never reading said video data from said second RAM during the updating of said video data; said interface means also writing said updated video data into both of said first and said second RAMs simultaneously.

Claim 19

A computer comprising a central processing unit CPU); a first random-access memory (RAM) coupled to said CPU; a second random-access memory (RAM) coupled to said CPU, said first and said second RAMs both storing the same video data, second RAM being accessed at a faster rate as compared to said second RAM; video circuits for providing video signals for a video display, said video signals being developed from said video data stored in said second RAM, said second RAM being coupled to said video circuits; CPU interface means for providing control between said CPU and said first and second RAMs, said interface means providing a control signal to said CPU and said first and second RAMs to selectively control access of said CPU to said RAMs such that when said control signal is in one state said video circuitry reads said second RAM to provide said video signal to said display, and when said control signal is in another state said CPU reads said first RAM to update said video data, said CPU never reading said video data from said second RAM during the updating of said video data; said interface means also writing said updated video data into both of said first and said second RAMs simultaneously.