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US4959814A
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Sensing detection circuit in dynamic random access memory
Assignee: Samsung Electronics Co Ltd
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Filing: 1988-12-28
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Granted: 1990-09-25
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Expires: 2008-12-28
Abstract
Abstract A sensing detection circuit in a DRAM detects the sensing of data in a memory array. The circuit reduces the sensing access time significantly by detecting an output produced upon completion of the data sensing in the memory array which output is used to immediately initiate the next date operation without unnecessary delay.
Inventors
- 👤 Soo I. Cho
- 👤 Si D. Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:40
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
115 words
A sensing detection circuit for a memory comprising: a first clock signal generator (CG1) responsive to an input signal for generating a clock signal; a sensing clock signal generator (SCG) controlled by said first clock signal generator (CG1) for supplying a sensing signal (S1) to a memory array (1); a sensing detector (SD) for detecting a first output signal (S2) from said memory array signifying the completion of the sensing of data from said memory array (1) and generating, in response to said first output signal, a second output signal (OUT) and; a second clock signal generator (CG2) responsive to said second output signal from said sensing detector (SD) for generating a successive clock signal.
Claim 2
Dependent Claim
115 words
A sensing detection circuit for a memory comprising: a first clock signal generator (CG1) responsive to an input signal for generating a clock signal; a sensing clock signal generator (SCG) controlled by said first clock signal generator (CG1) for supplying a sensing signal (S1) to a memory array (1); a sensing detector (SD) for detecting a first output signal (S2) from said memory array signifying the completion of the sensing of data from said memory array (1) and generating, in response to said first output signal, a second output signal (OUT) and; a second clock signal generator (CG2) responsive to said second output signal from said sensing detector (SD) for generating a successive clock signal.
Claim 3
Dependent Claim
72 words
A sensing detection circuit according to claim 1, wherein said memory array (1) includes a pair of bit lines (BL and BL) and a memory cell (2) including a transistor (M1) and a capacitor (C1) operated by a work line select signal, the voltage level of said bit lines (BL and BL) being changed by charging and discharging the capacitor (C1) through the transistor (M1) for generating said first output signal (S2).
Claim 4
Dependent Claim
118 words
A sensing detection circuit according to claim 2, wherein said memory array (1) further includes a pair of series connected P type MOS transistors (M2 and M3) and a pair of series connected N type MOS transistors (M4 and M5) each pair of which is connected between said pair of bit lines, a first node between said P type transistors being connected to a latch restore signal (LA), and the output signal of a third clock signal generator (S2CG) being connected to a second node between said N type transistors, and said first output signal being generated at said second node in response to the operation of said pairs of transistors under the control of said bit lines.
Claim 5
Dependent Claim
60 words
A sensing detection circuit according to claim 1, wherein said sensing detector (SD) includes P type MOS transistors (M10 and M11) for supplying a source of voltage (Vcc), P and N type MOS transistors (M12 and M13) for receiving said first output signal (S2), and P and N type MOS transistors (M14 and M15) for providing said second output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-24 | 1994-03-26 | 1994-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-24 | 1998-03-26 | 1998-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-24 | 2002-03-26 | 2002-09-25 | $7700.00 | Window Closed / Lapsed |