Patent US818933A successfully refreshed from Google Patents.
Patent US4959844A successfully refreshed from Google Patents.
US4959844A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock recovery circuit for digital demodulator
Assignee: TE Connectivity Corp
•
Filing: 1989-10-24
•
Granted: 1990-09-25
•
Expires: 2009-10-24
Abstract
Abstract A digital demodulator (10) operates by multiplying an input signal with first and second orthogonal demodulation reference signals (Loa, LOb) to generate respective product signals, which are then integrated to generate first and second integrated values (a, b) indicative of digital data encoded in the input signal. These integrated values (a, b) are digitized to generate first and second digital values (a, b). A first error signal a-a) indicative of the difference between the first integrated value (a) and the first digital value (a) is generated, and the first error signal (a-a) is combined with the second digital value (b) to generate a first feedback signal. This first feedback signal is utilized to generate a control signal (ab-ba) indicative of phase difference between the input signal and the demodulation reference signals (LOa, LOb).
Inventors
- 👤 Patrick K. Walp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:08
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/02; H04L5/12; H04L27/00; H04L27/26; H04L27/2601; H04L27/2647; H04L27/2655; H04L27/2657; H04L27/32; H04L27/34; H04L27/38; H04L27/3818
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
134 words
In a digital demodulator of the type comprising means for multiplying an input signal with first and second orthogonal demodulation reference signals to generate respective product signals, means for integrating the product signals to generate first and second integrated values indicative of digital data encoded in the input signal, and means for digitizing the integrated values to generate first and second digital values, the improvement comprising: first means for generating a first error signal indicative of the difference between the first integrated value and the first digital value; second means for combining the first error signal with the second digital value to generate a first feedback signal; third means for utilizing the first feedback signal to generate a control signal indicative of a phase difference between the input signal and the demodulation reference signals.
Claim 2
Dependent Claim
134 words
In a digital demodulator of the type comprising means for multiplying an input signal with first and second orthogonal demodulation reference signals to generate respective product signals, means for integrating the product signals to generate first and second integrated values indicative of digital data encoded in the input signal, and means for digitizing the integrated values to generate first and second digital values, the improvement comprising: first means for generating a first error signal indicative of the difference between the first integrated value and the first digital value; second means for combining the first error signal with the second digital value to generate a first feedback signal; third means for utilizing the first feedback signal to generate a control signal indicative of a phase difference between the input signal and the demodulation reference signals.
Claim 3
Dependent Claim
72 words
The invention of claim 1 wherein the third means comprises: fourth means for generating a second error signal indicative of the difference between the second integrated value and the second digital value; fifth means for combining the second error signal with the first digital value to generate a second feedback signal; and sixth means for generating the control signal as a function of the difference between the first and second feedback signals.
Claim 4
Dependent Claim
22 words
The invention of claim 1 wherein the second means comprises means for multiplying the first error signal by the second digital value.
Claim 5
Dependent Claim
22 words
The invention of claim 2 wherein the fifth means comprises means for multiplying the second error signal by the first digital value.
Claim 6
Dependent Claim
22 words
The invention of claim 2 wherein the sixth means comprises means for subtracting the second feedback signal from the first feedback signal.
Claim 7
Dependent Claim
29 words
The invention of claim 1 wherein the first and second reference signals each comprise at least one sinusoidally modulated component and differ from one another in phase by 90°.
Claim 8
Dependent Claim
16 words
The invention of claim 1 wherein the digitizing means digitizes the integrated values to four levels.
References Cited (Backward Citations)
US4344176A
Cited
US4458356A
Cited
US4535459A
Cited
US4649551A
Cited
US4689581A
Cited
US4625180A
Cited
US4687999A
Cited
US4667170A
Cited
US4677395A
Cited
US4809306A
Cited
US4712077A
Cited
US4862104A
Cited
US4879728A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-24 | 1994-03-26 | 1994-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-24 | 1998-03-26 | 1998-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-24 | 2002-03-26 | 2002-09-25 | $7700.00 | Window Closed / Lapsed |