Patent US4964037A successfully refreshed from Google Patents.
US4964037A
Expired / Lapsed
US
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Memory addressing arrangement
Assignee: Bull HN Information Systems Inc
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Filing: 1987-02-27
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Granted: 1990-10-16
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Expires: 2007-02-27
Abstract
Abstract A memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to indicate to the controller if the address is to be modified. The same address is applied unchanged to the addressing input of the other of the two memories by the memory address controller. In this manner the addressing range is expanded.
Inventors
- 👤 William E. Woods
- 👤 Richard A. Lemay
- 👤 David A. Wallace
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:00
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
314 words
An memory for use in an electronic data processing system which comprises, in combination, first and second random access memories each having an address input and a data port, each of said memories being capable of storing fixed length units of binary data at addressable storage locations specified by addresses applied to said address input, means for writing data into said first and second memories comprising a source of a sequence of units of data and a source of a sequence of address values corresponding to said units, and means for writing units associated with even-numbered addresses into said first memory and for writing units associated with odd-numbered addresses into said second memory, and means for reading units of data from said memory comprising, in combination, a source of address values, and means for concurrently applying first and second addresses to the address inputs of said first and second memories to permit units of data to be read concurrently from said first and second memories, said first and said second addresses being derived from the high-order bits of each given address value from said source such that, when said given address is even-numbered said first and second addresses are equal in value and, when said given address value is odd-numbered said first address is incremented by one, thereby insuring that the unit specified by said given address and the unit specified by said given address plus one are always read concurrently from said first and second memories; wherein each of said fixed length units of data comprises a pair of eight-bit bytes, and wherein the least significant bit value of each of said address values specifies the particular eight-bit byte within a particular unit and the next-to-least significant digit specifies whether the unit address is odd or even, and the remainder of said address value is used to generate said first and second addresses.
Claim 2
Dependent Claim
314 words
An memory for use in an electronic data processing system which comprises, in combination, first and second random access memories each having an address input and a data port, each of said memories being capable of storing fixed length units of binary data at addressable storage locations specified by addresses applied to said address input, means for writing data into said first and second memories comprising a source of a sequence of units of data and a source of a sequence of address values corresponding to said units, and means for writing units associated with even-numbered addresses into said first memory and for writing units associated with odd-numbered addresses into said second memory, and means for reading units of data from said memory comprising, in combination, a source of address values, and means for concurrently applying first and second addresses to the address inputs of said first and second memories to permit units of data to be read concurrently from said first and second memories, said first and said second addresses being derived from the high-order bits of each given address value from said source such that, when said given address is even-numbered said first and second addresses are equal in value and, when said given address value is odd-numbered said first address is incremented by one, thereby insuring that the unit specified by said given address and the unit specified by said given address plus one are always read concurrently from said first and second memories; wherein each of said fixed length units of data comprises a pair of eight-bit bytes, and wherein the least significant bit value of each of said address values specifies the particular eight-bit byte within a particular unit and the next-to-least significant digit specifies whether the unit address is odd or even, and the remainder of said address value is used to generate said first and second addresses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-15 | 1994-04-16 | 1994-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-15 | 1998-04-16 | 1998-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-15 | 2002-04-16 | 2002-10-16 | $7700.00 | Window Closed / Lapsed |