US4971925A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Improved method of manufacturing a semiconductor device of the "semiconductor on insulator" type
Assignee: US Philips Corp
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Filing: 1988-01-11
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Granted: 1990-11-20
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Expires: 2008-01-11
Abstract
Abstract In a method of manufacturing a semiconductor device of the "semiconductor on insulator" type comprising at least one carrier body and a monocrystalline semiconductor body, in a major surface (2) of a monocrystalline semiconductor body (1) grooves (3) are provided having a predetermined depth. The surface provided with grooves is coated with a layer (4) of material resistant to polishing; and this layer is coated with a layer (5) of a chemomechanically polishable material having a layer thickness exceeding the groove depth, the latter layer (5) being polished to flatness and smoothness. The polished surface of the semiconductor body (1) is connected to a smooth flat major surface of a carrier body (6). Subsequently, the semiconductor body (1) is made thin, at least the last part of this operation consisting of a polishing step, which terminates on the layer (4) of material resistant to polishing so that mutually insulated "semiconductor an insulator" regions are obtained, the thickness of the semiconductor regions being equal to the depth of the grooves.
Inventors
- 👤 Elizabeth M. L. Alexander
- 👤 Jan Haisma
- 👤 Theodorus Michielsen
- 👤 Johannes Van Der Velden
- 👤 Johannes F. C. M. Verhoeven
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:13
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/694; H10P14/6943; H10P14/69433; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/135; Y10S148/164
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
383 words
A method of manufacturing a semiconductor device of a "semiconductor on insulator" type comprising the steps of providing a monocrystalline semiconductor body with at least one flat optically smooth surface, forming a plurality of grooves in said flat smooth surface, said grooves having a predetermined depth, coating said surface having said grooves and coating said grooves with a first layer of material resistant to polishing, coating said first layer with a second layer of a chemomechanically polishable material, said second layer having a thickness greater than depths of said grooves, polishing said second layer down to said first layer at said flat smooth surface, said grooves with said first layer being filled with said chemomechanically polishable material of said second layer, forming a flat optically smooth surface of a carrier material, said optically smooth surface being provided with a layer of insulating material, joining said flat smooth surface of said carrier material to said first layer at said flat smooth surface on said semiconductor body, and polishing said semiconductor body at a side away from said carrier material down to said first layer of material resistant to polishing in said grooves, wherein semiconductor material of said semiconductor body remains between said plurality of grooves on said first layer, and wherein said second layer remains in said grooves surrounded by said first layer of material resistant to polishing and said layer of insulating material, and further comprising the steps of (a) forming IC structures in said semiconductor material remaining between said plurality of grooves, (b) depositing another layer of insulating material on said IC structures, (c) forming another layer of semiconductor material over said another layer of insulating material, said another layer of semiconductor material being interspersed with a further plurality of grooves, said another layer of semiconductor material having said first layer over a surface of said another layer of semiconductor material and on said further plurality of grooves and said second layer filling said further plurality of grooves, (d) forming another layer of IC structures in said another layer of semiconductor material between said further plurality of grooves in the same manner as said IC structures are formed in step (a), and (e) repeating steps (b) through (d) on said another layer of IC structures to form a tri-dimensional stack of IC's.
Claim 2
Independent Claim
383 words
A method of manufacturing a semiconductor device of a "semiconductor on insulator" type comprising the steps of providing a monocrystalline semiconductor body with at least one flat optically smooth surface, forming a plurality of grooves in said flat smooth surface, said grooves having a predetermined depth, coating said surface having said grooves and coating said grooves with a first layer of material resistant to polishing, coating said first layer with a second layer of a chemomechanically polishable material, said second layer having a thickness greater than depths of said grooves, polishing said second layer down to said first layer at said flat smooth surface, said grooves with said first layer being filled with said chemomechanically polishable material of said second layer, forming a flat optically smooth surface of a carrier material, said optically smooth surface being provided with a layer of insulating material, joining said flat smooth surface of said carrier material to said first layer at said flat smooth surface on said semiconductor body, and polishing said semiconductor body at a side away from said carrier material down to said first layer of material resistant to polishing in said grooves, wherein semiconductor material of said semiconductor body remains between said plurality of grooves on said first layer, and wherein said second layer remains in said grooves surrounded by said first layer of material resistant to polishing and said layer of insulating material, and further comprising the steps of (a) forming IC structures in said semiconductor material remaining between said plurality of grooves, (b) depositing another layer of insulating material on said IC structures, (c) forming another layer of semiconductor material over said another layer of insulating material, said another layer of semiconductor material being interspersed with a further plurality of grooves, said another layer of semiconductor material having said first layer over a surface of said another layer of semiconductor material and on said further plurality of grooves and said second layer filling said further plurality of grooves, (d) forming another layer of IC structures in said another layer of semiconductor material between said further plurality of grooves in the same manner as said IC structures are formed in step (a), and (e) repeating steps (b) through (d) on said another layer of IC structures to form a tri-dimensional stack of IC's.
Claim 3
Dependent Claim
13 words
A method according to claim 1, wherein said first layer is silicon nitride.
Claim 4
Dependent Claim
14 words
A method according to claim 2, wherein said second layer consists of polycrystalline silicon.
Claim 5
Dependent Claim
23 words
A method according to claim 3, wherein a third layer of a densified silicon dioxide is provided between said first and second layers.
Claim 6
Dependent Claim
15 words
A method according to claim 1, wherein said first layer consists of densified silicon dioxide.
Claim 7
Dependent Claim
16 words
A method according to claim 1 or 5, wherein said second layer consists of polycrystalline silicon.
Claim 8
Dependent Claim
20 words
A method according to claim 1 or 2 or 5, wherein said second layer consists of an undensified silicon dioxide.
Claim 9
Dependent Claim
20 words
A method according to claim 1, wherein said layer of insulating material is formed with a thickness of 1 μm.
Claim 10
Dependent Claim
19 words
A method according to claim 1 or 1 wherein said layer of insulating material is thermally grown silicon dioxide.
Claim 11
Dependent Claim
27 words
A method according to claim 1 wherein said semiconductor material between said plurality of grooves is formed with a thickness ranging from about 0.1 to 3 μm.
Claim 12
Dependent Claim
24 words
A method according to claim 1 wherein said semiconductor material between said plurality of grooves is formed to a thickness of about 5 μm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-19 | 1994-05-21 | 1994-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-19 | 1998-05-21 | 1998-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-19 | 2002-05-21 | 2002-11-20 | $7700.00 | Window Closed / Lapsed |