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Patent US4972467A successfully refreshed from Google Patents.
US4972467A
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Echo canceller
Assignee: NEC Corp
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Filing: 1988-07-20
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Granted: 1990-11-20
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Expires: 2008-07-20
Abstract
Abstract An echo canceller includes a first transversal filter for generating a first echo canceling signal to be canceled from an output signal from a sampler, the first echo canceling signal corresponding to a first sampling value of an echo response waveform of an echo path by a sampling clock when no sampling clock jitter occurs, a second transversal filter for generating a second echo canceling signal corresponding to a difference between the first sampling value and a second sampling value when the sampling clock jitter occurs, two subtractors for canceling the first and second echo canceling signals from a digital reception signal output from the sampler, and a controller for detecting the sampling clock jitter and performing a control operation such that a tap coefficient value of the second filter is added to a tap coefficient value of the first filter to update the tap coefficient value of the first filter, and thereafter, the second echo canceling signal generating operation of the second filter is disabled.
Inventors
- 👤 Fujio Nakagawa
- 👤 Akira Kanemasa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:46
CPC Classifications
H; H04; H04B; H04B3/00; H04B3/02; H04B3/20; H04B3/23; H04B3/237; H04B3/238
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
225 words
An echo canceller, comprising: an echo path comprising a D/A converter for converting a digital transmission signal into an analog signal, a hybrid circuit for transmitting the output from said D/A converter onto a transmission path, and receiving and outputting an analog reception signal from said transmission path to a path different from said transmission path, and a sampler for sampling the reception signal and outputting the sampled signal as a digital reception signal; a first transversal filter which has a first tap coefficient representing an echo path response wave at a fixed sampling time and which generates a first echo canceling signal; a second transversal filter which has a second tap coefficient representing a deviation of sampled values of said echo path response wave and generates a second echo canceling signal; subtracting means for subtracting said first and second echo canceling signals from said digital reception signal; and control means for detecting a sampling clock jitter and performing a control operation such that the second echo canceling signal generating operation of said second filter is enabled when said sampling clock jitter occurs, a value of said second tap coefficient is added to a value of said first tap coefficient of to update said value of said first tap coefficient, and thereafter, the second echo canceling signal generating operation of said second filter is disabled.
Claim 2
Dependent Claim
225 words
An echo canceller, comprising: an echo path comprising a D/A converter for converting a digital transmission signal into an analog signal, a hybrid circuit for transmitting the output from said D/A converter onto a transmission path, and receiving and outputting an analog reception signal from said transmission path to a path different from said transmission path, and a sampler for sampling the reception signal and outputting the sampled signal as a digital reception signal; a first transversal filter which has a first tap coefficient representing an echo path response wave at a fixed sampling time and which generates a first echo canceling signal; a second transversal filter which has a second tap coefficient representing a deviation of sampled values of said echo path response wave and generates a second echo canceling signal; subtracting means for subtracting said first and second echo canceling signals from said digital reception signal; and control means for detecting a sampling clock jitter and performing a control operation such that the second echo canceling signal generating operation of said second filter is enabled when said sampling clock jitter occurs, a value of said second tap coefficient is added to a value of said first tap coefficient of to update said value of said first tap coefficient, and thereafter, the second echo canceling signal generating operation of said second filter is disabled.
Claim 3
Dependent Claim
101 words
An echo canceller according to claim 1, wherein said subtracting means for subtracting the first and second echo canceling signals from said digital reception signal comprises first subtraction means for subtracting said second echo canceling signal from said digital reception signal, a third filter for filtering the output of said first subtraction means, second subtraction means for subtracting said first echo canceling signal from the output of said third filter, and transferring means for transferring said value of said second tap coefficient to said first filter through a fourth filter having the same transfer function as that of said third filter.
Claim 4
Dependent Claim
64 words
An echo canceller according to claim 1, wherein said control means comprises a detector for detecting a direction of a deviation of a sampling clock, and a controller for outputting a signal representing the direction of the deviation, and said second filter comprises multiplying means for multiplying said second tap coefficient with said signal representing the direction of the deviation of the sampling clock.
Claim 5
Dependent Claim
64 words
An echo canceller according to claim 2, wherein said control means comprises a detector for detecting a direction of a deviation of a sampling clock, and a controller for outputting a signal representing the direction of the deviation, and said second filter comprises multiplying means for multiplying said second tap coefficient with said signal representing the direction of the deviation of the sampling clock.
References Cited (Backward Citations)
US4695998A
Cited
EP0192359A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-19 | 1994-05-21 | 1994-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-19 | 1998-05-21 | 1998-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-19 | 2002-05-21 | 2002-11-20 | $7700.00 | Window Closed / Lapsed |