Programmable quiesce apparatus for retry, recovery and debug

Claim 2

In a processing system including independently-clocked central processing and I/O control processing units, a memory, and an address/data/control (ADC) bus for coupling at least one I/O device to said I/O control processing unit, said I/O control processing unit for processing system I/O instructions to enable information transfer on said ADC bus, said I/O control processing unit having an instruction processor, a control store, an I/O clock source, control logic, a control register, an ADC bus arbiter; said control logic for selecting instructions from said control store for transfer to said control register with said control logic for controlling the transfer of instructions to said control store, said instruction processor for executing instructions in said control register for controlling the transfer of information between said central processing unit and said I/O control processing unit, between said memory and said I/O control processing unit, and on said ADC bus with said ADC bus arbiter arbitrating ADC bus requests and providing ADC bus access to each request bus user according to a predetermined hierarchy, said I/O control processing unit having an apparatus for, in response to an error indication, suspending I/O control processing unit operation in a known state, and suspending ADC bus arbiter operation so as to inhibit ADC bus access to requesting users, said apparatus comprising: quiesce means responsive to an error indication for generating a quiesce signal indicative of a quiesce condition; no operation (NOP) means connected to said quiesce means and said control register, said NOP means for generating a no operation (NOP) instruction and responsive to said quiesce signal for loading said NOP instruction into said control register; and wherein said instruction processor repeatedly executes said NOP instruction during said quiesce condition.

Claim 3

The apparatus of claim 1 wherein said NOP means is further responsive to said quiesce signal for loading said NOP instruction into said control register upon completion of execution of a current instruction in said control register.

Claim 4

The apparatus of claim 1 wherein said quiesce means is connected to said ADC bus arbiter for providing said ADC bus arbiter with said quiesce signal so as to suspend ADC bus arbiter operation.

Claim 5

In a computing system including a processor for executing instructions, a control register in said processor for receiving instructions to be executed by said processor, a bi-direction bus connected to said processor, and an arbiter in said processor for allocating use of said bi-directional bus in response to bus use requests, an improvement for suspending the operation of said processor in response to error and quiesce conditions which are indicated by a quiesce conditioning signal, said improvement comprising, in combination: instruction control logic connected to said control register for producing an instruction loading signal in response to a first instruction in said control register; a quiesce means for activating a quiesce signal in response to said quiesce conditioning signal; control register circuit means connected to said control register, said instruction control logic, and said quiesce means for loading a NOP instruction into said control register in response to said instruction loading signal and to said activation of said quiesce signal; and means in said bus arbiter and connected to said quiesce means for suspending allocation of use of said bi-directional bus in response to said quiesce signal.

Claim 6

In a computing system including a processor for executing instructions, a control register in said processor for receiving instructions to be executed by said processor, a bi-direction bus connected to said processor, and an arbiter in said processor for allocating use of said bi-directional bus in response to bus use requests, an improvement for suspending the operation of said processor in response to error and quiesce conditions which are indicated by a quiesce conditioning signal, said improvement comprising, in combination: instruction control logic connected to said control register for producing an instruction loading signal in response to a first instruction in said control register; a quiesce means for activating a quiesce signal in response to said quiesce conditioning signal; control register circuit means connected to said control register, said instruction control logic, and said quiesce means for loading a NOP instruction into said control register in response to said instruction loading signal and to said activation of said quiesce signal; and means in said bus arbiter and connected to said quiesce means for suspending allocation of use of said bi-directional bus in response to said quiesce signal.

Claim 7

In a computing system including a first and second processor and a bi-directional bus connected to said second processor, said first processor including a first control register for receiving an instruction to be executed by said first and second processors and instruction control logic connected to said first control register for producing an instruction load signal in response to said instruction, and said second processor including a second control register for receiving said instruction and an arbiter for allocating access to said bi-directional bus, an improvement for suspending operations of said first and second processors in response to a condition signal indicating the presence of conditions requiring suspension of the operation of said first and second processors, wherein the improvement comprises: a quiesce means in said second processor for activating a quiesce signal in response to said condition signal; in said first processor: a first control circuit connected to said quiesce means and to said instruction control logic for producing a sequence of load signals in response to said instruction load signal and to said quiesce signal; and a NO OP circuit connected to said first control circuit and to said first control register and responsive to said sequence of load signals for entering a NOP instruction into said first control register and retaining said NOP instruction in said first control register; and, in said second processor; a second control circuit connected to said quiesce means and to said instruction control logic for producing a sequence of load signals in response to said instruction load signal and to said quiesce signal; a NO OP circuit connected to said second control circuit and to said second control register and responsive to said sequence of load signals for entering a NOP instruction into said second control register and retaining said NOP instruction in said second control register; and means in said arbiter and connected to said quiesce means for suspending access allocation of said bi-directional bus.

Claim 8

In a computing system including a first and second processor and a bi-directional bus connected to said second processor, said first processor including a first control register for receiving an instruction to be executed by said first and second processors and instruction control logic connected to said first control register for producing an instruction load signal in response to said instruction, and said second processor including a second control register for receiving said instruction and an arbiter for allocating access to said bi-directional bus, an improvement for suspending operations of said first and second processors in response to a condition signal indicating the presence of conditions requiring suspension of the operation of said first and second processors, wherein the improvement comprises: a quiesce means in said second processor for activating a quiesce signal in response to said condition signal; in said first processor: a first control circuit connected to said quiesce means and to said instruction control logic for producing a sequence of load signals in response to said instruction load signal and to said quiesce signal; and a NO OP circuit connected to said first control circuit and to said first control register and responsive to said sequence of load signals for entering a NOP instruction into said first control register and retaining said NOP instruction in said first control register; and, in said second processor; a second control circuit connected to said quiesce means and to said instruction control logic for producing a sequence of load signals in response to said instruction load signal and to said quiesce signal; a NO OP circuit connected to said second control circuit and to said second control register and responsive to said sequence of load signals for entering a NOP instruction into said second control register and retaining said NOP instruction in said second control register; and means in said arbiter and connected to said quiesce means for suspending access allocation of said bi-directional bus.