Semiconductor memory device

Claim 2

A semiconductor memory device comprising, a sense amplifier circuit for detecting a content of a memory cell selected from plural memory cells and producing a memory cell signal of high or low level dependent on said content, a reference voltage producing circuit for producing a reference voltage, and means for comparing said memory cell signal and said reference voltage to decide whether said content is "1" or "0", wherein said sense amplifier circuit includes means for setting a first predetermined voltage at a stand-by mode, and means for lowering said first predetermined voltage to a second predetermined voltage and then increasing said second predetermined voltage to said high or low level of said memory cell signal corresponding to said content of "1" or "0" in accordance with a first load characteristic thereof at a reading mode subsequent to said stand-by mode, and said reference voltage producing circuit includes means for setting a third predetermined voltage equal to said first predetermined voltage at said stand-by mode, and means for lowering said third predetermined voltage to said reference voltage in accordance with a second load characteristic which is different from said first load characteristic at said reading mode subsequent to said stand-by mode.

Claim 3

A semiconductor memory device according to claim 1, wherein said means for lowering of said reference voltage producing circuit provides a voltage drop equal to a median of a voltage difference between said high and low levels of said memory cell signal in accordance with said first and second load characteristics, and currents of the same level flowing through said means for lowering of said sense amplifier circuit and said reference voltage producing circuit.

Claim 4

A semiconductor memory device comprising, a sense amplifier circuit for detecting a content of a memory cell selected from plural memory cells and producing a memory cell signal of high or low level dependent on said content, said sense amplifier circuit including a first inverted amplifier having an input connected to a digit line of said memory cell, a first field effect transistor having a gate electrode connected to an output of said first inverted amplifier and a source electrode connected to said digit line, and a second field effect transistor positioned between a power supply and a drain electrode of said first field effect transistor and controlled to be constantly turned on in accordance with a gate potential, a reference voltage producing circuit for producing a reference voltage, said reference voltage producing circuit including a third field effect transistor having a drain electrode connected to a predetermined node therein and a source electrode connected to ground and turned on at a reading mode, a second inverted amplifier having an input connected to said predetermined node and having the same input and output characteristics as those of said first inverted amplifier, a fourth field effect transistor having a gate electrode connected to an output of said second inverted amplifier, a source electrode connected to said predetermined node and having the same device dimension as that of said first field effect transistor, and a characteristic modifying circuit composed of plural field effect transistors connected in parallel and positioned between a power supply and a drain electrode of said fourth field effect transistor, each of said plural field effect transistors having the same device dimension as that of said second field effect transistor, and means for comparing said memory cell signal and said reference voltage to decide whether said content is "1" or "0".

Claim 5

A semiconductor memory device comprising, a sense amplifier circuit for detecting a content of a memory cell selected from plural memory cells and producing a memory cell signal of high or low level dependent on said content, said sense amplifier circuit including a first inverted amplifier having an input connected to a digit line of said memory cell, a first field effect transistor having a gate electrode connected to an output of said first inverted amplifier and a source electrode connected to said digit line, and a second field effect transistor positioned between a power supply and a drain electrode of said first field effect transistor and controlled to be constantly turned on in accordance with a gate potential, a reference voltage producing circuit for producing a reference voltage, said reference voltage producing circuit including a third field effect transistor having a drain electrode connected to a predetermined node therein and a source electrode connected to ground and turned on at a reading mode, a second inverted amplifier having an input connected to said predetermined node and having the same input and output characteristics as those of said first inverted amplifier, a fourth field effect transistor having a gate electrode connected to an output of said second inverted amplifier, a source electrode connected to said predetermined node and having the same device dimension as that of said first field effect transistor, and a characteristic modifying circuit composed of plural field effect transistors connected in parallel and positioned between a power supply and a drain electrode of said fourth field effect transistor, each of said plural field effect transistors having the same device dimension as that of said second field effect transistor, and means for comparing said memory cell signal and said reference voltage to decide whether said content is "1" or "0".