Floating-gate memory cell with tailored doping profile

Claim 2

A floating-gate memory device comprising: peripheral transistors and memory transistors, said peripheral transistors comprising n-channel devices, said memory transistors each comprising: a substrate having a p-type upper portion: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion: a gate oxide overlying said channel region, and a floating gate overlying said gate oxide: a control gate overlying and insulated from said floating gate: wherein the the largest value of the net p-type dopant concentration anywhere within the volume of said p-type upper portion extending from 0 to 0.5 microns directly below the interface between said gate oxide and said channel region is more than 1.5 times the net p-type dopant concentration in said channel region at the interface between said gate oxide and said channel region: and wherein the maximum value of net p-type doping concentration within the upper portion of said substrate occurs at a depth which is shallower than the depth of said source/drain diffusions: and wherein the background value of net p-type doping concentration within the upper portion of said substrate near said memory transistors is greater than the background value of net p-type doping concentration within the upper portion of said substrate near said n-channel peripheral transistors.

Claim 3

The device of claim 1, wherein said floating gate is nowhere substantially thinner than said gate oxide.

Claim 4

The device of claim 1, wherein said first and second source/drain regions are each substantially overlain by an oxide which is at least three times as thick as said gate oxide.

Claim 5

The device of claim 1, wherein said first and second source/drain regions are each substantially exposed at the surface of said semiconductor upper portion, and wherein said channel region is bounded at the edges thereof, where not bounded by the respective source/drain regions, by a thick field isolation region.

Claim 6

The device of claim 1, wherein said substrate has a p-type background doping in upper portions thereof of at least 1E16 cm -3 .

Claim 8

A floating-gate memory device comprising: peripheral transistors and memory transistors, said peripheral transistors comprising n-channel devices, said memory transistors each comprising: a substrate having a p-type upper portion: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion: a gate oxide overlying said channel region, and a floating gate overlying said gate oxide: a control gate overlying and insulated from said floating gate: wherein the largest value of the net p-type dopant concentration anywhere within the volume of said p-type upper portion extending from 0 to 0.5 microns directly below the interface between said gate oxide and said channel region is more than 1.5 times the net p-type dopant concentration in said channel region at the interface between said gate oxide and said channel region and is also more than twice the net p-type background dopant concentration in the substrate upper portion: and wherein the maximum value of net p-type doping concentration within the upper portion of said substrate occurs at a depth which is shallower than the depth of said source/drain diffusions: and wherein the background value of net p-type doping concentration within the upper portion of said substrate near said memory transistors is equal to or greater than the background value of of net p-type doping concentration within the upper portion of said substrate near said n-channel peripheral transistors.

Claim 9

A floating-gate memory device comprising: peripheral transistors and memory transistors, said peripheral transistors comprising n-channel devices, said memory transistors each comprising: a substrate having a p-type upper portion: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion: a gate oxide overlying said channel region, and a floating gate overlying said gate oxide: a control gate overlying and insulated from said floating gate: wherein the largest value of the net p-type dopant concentration anywhere within the volume of said p-type upper portion extending from 0 to 0.5 microns directly below the interface between said gate oxide and said channel region is more than 1.5 times the net p-type dopant concentration in said channel region at the interface between said gate oxide and said channel region and is also more than twice the net p-type background dopant concentration in the substrate upper portion: and wherein the maximum value of net p-type doping concentration within the upper portion of said substrate occurs at a depth which is shallower than the depth of said source/drain diffusions: and wherein the background value of net p-type doping concentration within the upper portion of said substrate near said memory transistors is equal to or greater than the background value of of net p-type doping concentration within the upper portion of said substrate near said n-channel peripheral transistors.

Claim 10

The device of claim 7, wherein said floating gate is nowhere substantially thinner than said gate oxide.

Claim 11

The device of claim 7, wherein said first and second source/drain regions are each substantially overlain by an oxide which is at least three times as thick as said gate oxide.

Claim 12

The device of claim 7, wherein said first and second source/drain regions are each substantially exposed at the surface of said semiconductor upper portion, and wherein said channel region is bounded at the edges thereof, where not bounded by the respective source/drain regions, by a thick field isolation region.

Claim 13

The device of claim 7, wherein said substrate has a p-type background doping in upper portions thereof of at least 1E16 cm -3 .

Claim 15

A floating-gate memory device comprising: a substrate having a p-type upper portion: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion: a gate oxide overlying said channel region, and a floating gate overlying said gate oxide: a control gate overlying and insulated from said floating gate: wherein said upper portion of said substrate directly beneath said gate oxide includes both atoms of a p-type dopant species and atoms of an n-type dopant species, said p-type dopant species and said n-type dopant species having vertical concentration profiles such that the depth at which the concentration of said p-type dopant species declines to 50% less than its near-surface peak value is more than two times the depth at which the concentration of said n-type dopant species declines to 50% less than its near-surface peak value.

Claim 16

A floating-gate memory device comprising: a substrate having a p-type upper portion: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion: a gate oxide overlying said channel region, and a floating gate overlying said gate oxide: a control gate overlying and insulated from said floating gate: wherein said upper portion of said substrate directly beneath said gate oxide includes both atoms of a p-type dopant species and atoms of an n-type dopant species, said p-type dopant species and said n-type dopant species having vertical concentration profiles such that the depth at which the concentration of said p-type dopant species declines to 50% less than its near-surface peak value is more than two times the depth at which the concentration of said n-type dopant species declines to 50% less than its near-surface peak value.

Claim 17

The device of claim 13, wherein said p-type dopant is boron and said n-type dopant is predominantly arsenic.

Claim 18

The device of claim 13, wherein said n-type dopant is arsenic.

Claim 19

The device of claim 13, wherein said n-type dopant is antimony.

Claim 20

The device of claim 13, wherein said p-type dopant is boron.

Claim 21

The device of claim 13. wherein the net p-type dopant concentration of said upper portion of said substrate at locations sufficiently far from said gate oxide that said p-type dopant concentration has declined to approximately a uniform level is in the range of 5E15 cm -3 to 1.5E16 cm -3 , inclusive.

Claim 22

The device of claim 13, wherein the depth of said source/drain diffusions is in the range of 0.4 to 0.8 microns inclusive.

Claim 23

The device of claim 13, wherein said floating gate is nowhere substantially thinner than said gate oxide.

Claim 24

The device of claim 13, wherein said first and second source/drain regions are each substantially overlain by an oxide which is at least three times as thick as said gate oxide.

Claim 25

The device of claim 13, wherein said first and second source/drain regions are each substantially exposed at the surface of said semiconductor upper portion, and wherein said channel region is bounded at the edges thereof, where not bounded by the respective source/drain regions, by a thick field isolation region.

Claim 26

The device of claim 13, wherein said substrate has a p-type background doping in upper portions thereof of at least 1E16 cm -3 .

Claim 28

A floating-gate memory device comprising: a substrate having a p-type upper portion: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion: a gate oxide overlying said channel region, and a floating gate overlying said gate oxide: a control gate overlying and insulated from said floating gate; wherein said upper portion of said substrate directly beneath said gate oxide includes both atoms of a p-type dopant species and atoms of an n-type dopant species, said p-type dopant species and said n-type dopant species having vertical concentration profiles such that the depth at which the concentration of said p-type dopant species declines to 50% less than its near-surface peak value is more than two times the depth at which the concentration of said n-type dopant species declines to 50% less than its near-surface peak value, and the depth at which the concentration of said p-type dopant species declines to 50% less than its near-surface peak value is less than two times the depth of said source/drain diffusions.

Claim 29

A floating-gate memory device comprising: a substrate having a p-type upper portion: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion: a gate oxide overlying said channel region, and a floating gate overlying said gate oxide: a control gate overlying and insulated from said floating gate; wherein said upper portion of said substrate directly beneath said gate oxide includes both atoms of a p-type dopant species and atoms of an n-type dopant species, said p-type dopant species and said n-type dopant species having vertical concentration profiles such that the depth at which the concentration of said p-type dopant species declines to 50% less than its near-surface peak value is more than two times the depth at which the concentration of said n-type dopant species declines to 50% less than its near-surface peak value, and the depth at which the concentration of said p-type dopant species declines to 50% less than its near-surface peak value is less than two times the depth of said source/drain diffusions.

Claim 30

The device of claim 25, wherein said p-type dopant is boron and said n-type dopant is predominantly arsenic.

Claim 31

The device of claim 25, wherein said n-type dopant is arsenic.

Claim 32

The device of claim 25, wherein said n-type dopant is antimony.

Claim 33

The device of claim 25, wherein said p-type dopant is boron.

Claim 34

The device of claim 25. wherein the net p-type dopant concentration of said upper portion of said substrate at locations sufficiently far from said gate oxide that said p-type dopant concentration has declined to approximately a uniform level is in the range of 8E15 cm -3 to 1.5E16 cm -3 , inclusive.

Claim 35

The device of claim 25, wherein the depth of said source/drain diffusions is in the range of 0.4 to 0.8 microns inclusive.

Claim 36

The device of claim 25, wherein said floating gate is nowhere substantially thinner than said gate oxide.

Claim 37

The device of claim 25, wherein said first and second source/drain regions are each substantially overlain by an oxide which is at least three times as thick as said gate oxide.

Claim 38

The device of claim 25, wherein said first and second source/drain regions are each substantially exposed at the surface of said semiconductor upper portion, and wherein said channel region is bounded at the edges thereof, where not bounded by the respective source/drain regions, by a thick field isolation region.

Claim 39

The device of claim 25, wherein said substrate has a p-type background doping in upper portions thereof of at least 1E16 cm -3 .