N×M round robin order arbitrating switching matrix system

Claim 2

A N×M switching matrix system with arbitration comprising: M outputs ports; N data inputs and request inputs from different sources, each request input associated with a data input and indicating which of M output ports the associated data is to be applied; M arbitrators and M gating means, each arbitrator and associated gating means is coupled between said N data inputs and request inputs and a different one of said M output ports; and each of said arbitrator and gating means being responsive to said data inputs and request inputs for gating data input simultaneously to the requested output port when there is no contending request inputs for the same output port and for when there is contending request inputs for the same output port storing and sequencing the associated data inputs from said different sources to the associated output port on a round robin basis while simultaneously applying the non contending data inputs to the other output ports.

Claim 3

The system of claim 1 wherein the M arbitrators and M gating means include logic means which have a priority sequence for beginning the gating of the contending request signals out of the gating means.

Claim 4

The combination of claim 1 wherein the arbitrator means includes logic means producing a coded signal to the gating means which identifies the request input and said gating means is coupled directly to said data inputs and in response to said code signal from said aribtrator gates that input to the associated output port.

Claim 5

A multi-processor system for coupling an N plurality of processors to an M plurality of basic storage modules (BSM) comprising: M basic storage modules; N processors, each providing a data packet and a request code signal identifying which basic storage module said data packet is to be applied; and M arbitrator and M gating means with an arbitrator and associated gating means coupled and associated with each of said basic storage modules with each arbitrator and gating means coupled between said N processors and a different one of said Basic Storage Modules; said arbitrators and gating means responsive to said request signal and said data packet at its input for simultaneously gating associated data packets to its coupled basic storage module and when more than one request is received at a given cycle at any one of said arbitrators associated with basic storage module from said processors sequencing said data packets from said processors on a round robin basis to the associated basic storage module.

Claim 6

A multi-processor system for coupling an N plurality of processors to an M plurality of basic storage modules (BSM) comprising: M basic storage modules; N processors, each providing a data packet and a request code signal identifying which basic storage module said data packet is to be applied; and M arbitrator and M gating means with an arbitrator and associated gating means coupled and associated with each of said basic storage modules with each arbitrator and gating means coupled between said N processors and a different one of said Basic Storage Modules; said arbitrators and gating means responsive to said request signal and said data packet at its input for simultaneously gating associated data packets to its coupled basic storage module and when more than one request is received at a given cycle at any one of said arbitrators associated with basic storage module from said processors sequencing said data packets from said processors on a round robin basis to the associated basic storage module.

Claim 7

The combination of claim 4 wherein said arbitrator means includes logic means sequencing said gating means in accordance with a given priority.

Claim 8

The combination of claim 5 wherein each of said arbitrators produces code signals and said gating means is responsive to said data packets and said arbitrator provided code indicative of the associated processor for gating the appropriate processor input to the Basic Storage Module.

Claim 9

The combination of claim 6 above including a FIFO buffer means coupled between said processors and said arbitrators and gating means for storing and sequencing said data packets and request signals from said processors each clock cycle on a first in first out basis.

Claim 10

The combination of claim 7 above wherein said first buffer means has at least M stages.

Claim 11

The combination of claim 8 above including a second buffer means between each gating means and associated Basic Storage Module.