Patent US5021685A successfully refreshed from Google Patents.
US5021685A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input buffer circuit having a resistor for reducing through-current and a capacitor for preventing delay
Assignee: Mitsubishi Electric Corp
•
Filing: 1990-04-13
•
Granted: 1991-06-04
•
Expires: 2010-04-13
Abstract
Abstract An input buffer for semiconductor integrated circuits has a resistor (16), capacitor (17) and a logical gate comprising transistors (11, 12, 13) connected in series between a supply line (61) and a ground line (62). The resistor (16) reduces the through current which flows toward the ground (Vss) when the logical gate switches. In a high speed operation, the capacitor (17) supplies current to the logical gate so that any delay which may possibly be caused by the provision of the resistor (16) can be prevented.
Inventors
- 👤 Yuji Kihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:18
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
94 words
An input buffer circuit for semiconductor integrated circuits which can operate in a predetermined operation cycle, comprising: resistance means and logical gate means connected in series between first supply potential and second supply potential, said logical gate means operating in response to an input signal; and capacitance means connected between a connection node of said resistance means and logical gate means, and said second supply potential, the time constant defined by said resistance means and capacitance means for charging said capacitance means being set to be below a value defined by said operation cycle.
Claim 2
Dependent Claim
94 words
An input buffer circuit for semiconductor integrated circuits which can operate in a predetermined operation cycle, comprising: resistance means and logical gate means connected in series between first supply potential and second supply potential, said logical gate means operating in response to an input signal; and capacitance means connected between a connection node of said resistance means and logical gate means, and said second supply potential, the time constant defined by said resistance means and capacitance means for charging said capacitance means being set to be below a value defined by said operation cycle.
Claim 3
Dependent Claim
45 words
The input buffer circuit for semiconductor integrated circuits according to claim 1, wherein the threshold value of said logical gate means is set to be a value closer to said second potential with respect to an intermediate value between said first and second supply potentials.
Claim 4
Dependent Claim
22 words
The input buffer circuit for semiconductor integrated circuits according to claim 2, wherein said logical gate means comprises first inverter means means.
Claim 5
Dependent Claim
34 words
The input buffer circuit for semiconductor integrated circuits according to claim 2, wherein the threshold value of said logical gate means is compatible with a logical level of an externally provided transistor-transistor logic circuit.
Claim 6
Dependent Claim
21 words
The input buffer circuit for semiconductor integrated circuits according to claim 2, wherein said logical gate means comprises NOR gate means.
Claim 7
Dependent Claim
75 words
The input buffer circuit for semiconductor integrated circuits according to claim 3, wherein said first inverter means comprises: first field effect device of one conductivity type having a control electrode and second field effect device of the opposite conductivity type having a control electrode which are connected in series between the first and second supply potentials, the control electrodes of said first and second field effect devices being connected together to receive the input signal.
Claim 8
Dependent Claim
87 words
The input buffer circuit for semiconductor integrated circuits according to claim 5, wherein said NOR gate means comprises: third field effect device of one conductivity type having a control electrode; and second inverter means connected with said third field effect device in series between the first and second supply potentials, said third field effect device having the control electrode connected to receive a control signal for externally controlling said input buffer circuit, and said second inverter means having an input node connected to receive the input signal.
Claim 9
Dependent Claim
25 words
The input buffer circuit for semiconductor integrated circuits according to claim 1, wherein said predetermined value defined by said operating cycle comprises 10 -8 sec.
Claim 10
Dependent Claim
43 words
The input buffer circuit for semiconductor integrated circuits according to claim 6, wherein said field effect device of one conductivity type includes a p-type field effect device, and said field effect device of the opposite conductivity type includes an n-type field effect device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-03 | 1994-12-03 | 1995-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-03 | 1998-12-03 | 1999-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-03 | 2002-12-03 | 2003-06-04 | $7700.00 | Window Closed / Lapsed |