Digital image processing apparatus for correctly addressing image memory

Claim 2

A digital image processing apparatus comprising: an image input circuit for inputting image data; an image output circuit for outputting image data; a plurality of image memories for storing image data; a plurality of processing circuits capable of pipeline processing image data; an image data bus for transferring image data between each of said circuits in accordance with a transfer clock; an address counter generating a read address and a write address to be applied to said image memory; and an address bus for applying the address generated by said address counter to said image memory; wherein each of said processing circuits is structured such that a delay of n (n is a positive integer) transfer clocks or an integer multiple of n clocks is generated between the input and output data; said address counter comprises a read address counter which is counted up at a period of n transfer clocks, and a delay circuit array having multi stages of delay circuits, each generating a delay of n transfer clocks, cascade connected to generate a plurality of write addresses from a read address inputted to said delay circuit of a first stage; and said image memory comprises a write address selecting circuit which selects, when a delay time of a write data is Kxn transfer clocks (K is a positive integer), a write address outputted from Kth one of said delay circuits; whereby the delay time of the whole processing circuit becomes the integer multiple of n transfer clocks regardless of the combination of the plurality of processing circuits and that the processing circuits can be freely coupled with each other.

Claim 3

A digital image processing apparatus according to claim 1, wherein said image memory comprises a shift register for writing converting n serial data on said image data bus to parallel data, n sets of memory devices in which parallel data outputted from said shift register for writing are simultaneously written, and a shift register for reading converting parallel data simultaneously read from said n sets of memory devices to n serial data to output the same on said image data bus.

Claim 4

A digital image processing apparatus according to claim 1, wherein a plurality of write addresses outputted from said delay circuit array are switched in synchronization with the transfer clock in a period of n transfer clocks to be time-division multiplexed on one write address bus.

Claim 5

A digital image processing apparatus according to claim 1, wherein said image output circuit comprises a variable length FIFO register provided at the input stage to maintain a number of delay stages of the output data at a constant value.

Claim 6

A digital image processing apparatus comprising: an image input circuit for inputting image data; an image output circuit for outputting image data; a plurality of image memories for storing image data; a processing circuit for processing image data; an image data bus for transferring image data between each of said circuits in accordance with a transfer clock; an address counter generating a read address and a write address to be applied to said image memory; and an address bus for applying the address generated by said address counter to said image memory; wherein said processing circuit is structured such that a delay of n (n is a positive integer) transfer clocks or an integer multiple of n clocks is generated between the input and output data; said address counter comprises a read address counter which is counted up at a period of n transfer clocks, and a delay circuit array having a plurality of delay circuits, cascade connected for generating a plurality of write addresses from a read address counted by read address counter, and said image memory comprises a write address selecting circuit which selects, when a delay time of a write data processed by said processing circuit is Kxn transfer clocks (K is a positive integer), a write address outputted from said delay circuits, said write address provided by shifting the read address by an amount corresponding to Kxn transfer clocks, whereby the delay time of the whole processing circuit becomes the integer multiple of n transfer clocks regardless of the combination of the plurality of processing circuits and that the processing circuits can be freely coupled with each other.

Claim 7

A digital image processing apparatus comprising: an image input circuit for inputting image data; an image output circuit for outputting image data; a plurality of image memories for storing image data; a processing circuit for processing image data; an image data bus for transferring image data between each of said circuits in accordance with a transfer clock; an address counter generating a read address and a write address to be applied to said image memory; and an address bus for applying the address generated by said address counter to said image memory; wherein said processing circuit is structured such that a delay of n (n is a positive integer) transfer clocks or an integer multiple of n clocks is generated between the input and output data; said address counter comprises a read address counter which is counted up at a period of n transfer clocks, and a delay circuit array having a plurality of delay circuits, cascade connected for generating a plurality of write addresses from a read address counted by read address counter, and said image memory comprises a write address selecting circuit which selects, when a delay time of a write data processed by said processing circuit is Kxn transfer clocks (K is a positive integer), a write address outputted from said delay circuits, said write address provided by shifting the read address by an amount corresponding to Kxn transfer clocks, whereby the delay time of the whole processing circuit becomes the integer multiple of n transfer clocks regardless of the combination of the plurality of processing circuits and that the processing circuits can be freely coupled with each other.

Claim 8

A digital image processing apparatus according to claim 5 in which said plurality of delay circuits are cascade connected, and each generating a delay of n transfer clocks, and said write address selecting circuit selects a write address outputted from Kth delay circuit.

Claim 9

A digital image processing apparatus according to claim 5 in which said processing circuit has a plurality of image processing elements, and is capable of pipeline processing image data.