Patent US5032889A successfully refreshed from Google Patents.
US5032889A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wiring structure in a wafer-scale integrated circuit
Assignee: Fujitsu VLSI Ltd
•
Filing: 1990-09-20
•
Granted: 1991-07-16
•
Expires: 2010-09-20
Abstract
Abstract A wafer-scale integrated circuit includes a plurality of functional blocks, a plurality of respectively corresponding connection terminals being provided in each of the functional blocks. Respectively corresponding pluralities of layered wirings and bonding wires interconnect predetermined, respective ones of said corresponding connection terminals in parallel for supplying power source and other voltages in common to the plurality of functional blocks. The parallel interconnections by the layered wirings and bonding wires, due to different, respective failure modes, affording increased reliability.
Inventors
- 👤 Toshiaki Murao
- 👤 Takeo Kikuchi
- 👤 Toshihiko Iryu
- 👤 Hiroyuki Sugamoto
- 👤 Hidenori Nomura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:23
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W72/00; H10W72/50; H10W72/071; H10W72/075; H10W72/07531; H10W72/07532; H10W72/07533; H10W72/541; H10W72/5453; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/90; H10W72/931; H10W72/932
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
95 words
A semiconductor wafer-scale integrated-circuit comprising: a single wafer; a plurality of functional blocks formed on said wafer; a plurality of respectively corresponding connection terminals provided in each of said functional blocks; a plurality of layered wirings interconnecting respective and predetermined ones of said respectively corresponding connection terminals of said plurality of functional blocks; and a plurality of bonding wires corresponding to said plurality of layered wirings and interconnecting the same said predetermined and respective ones of said connection terminals of said functional blocks, in addition to and electrically in parallel to said corresponding layered wirings.
Claim 2
Dependent Claim
95 words
A semiconductor wafer-scale integrated-circuit comprising: a single wafer; a plurality of functional blocks formed on said wafer; a plurality of respectively corresponding connection terminals provided in each of said functional blocks; a plurality of layered wirings interconnecting respective and predetermined ones of said respectively corresponding connection terminals of said plurality of functional blocks; and a plurality of bonding wires corresponding to said plurality of layered wirings and interconnecting the same said predetermined and respective ones of said connection terminals of said functional blocks, in addition to and electrically in parallel to said corresponding layered wirings.
Claim 3
Dependent Claim
53 words
A semiconductor wafer-scale integrated-circuit as recited in claim 1, wherein said connection terminals comprise supply voltage terminals of each said functional block, said plurality of corresponding layered wirings and bonding wires conducting respective supply voltages in common to the respective and predetermined connection terminals respectively interconnected thereby, and correspondingly to said functional blocks.
Claim 4
Dependent Claim
17 words
A semiconductor wafer-scale integrated-circuit as recited in claim 1, wherein said supply voltage is a power-source voltage.
Claim 5
Dependent Claim
18 words
A semiconductor wafer-scale integrated-circuit as recited in claim 1, wherein said supply voltage is a clock signal voltage.
Claim 6
Dependent Claim
20 words
A semiconductor wafer-scale integrated-circuit as recited in claim 1, wherein said plurality of functional blocks are identical with each other.
Claim 7
Dependent Claim
24 words
A semiconductor wafer-scale integrated-circuit as recited in claim 1, wherein each of said functional blocks is fabricated according to a step and repeat method.
Claim 8
Dependent Claim
26 words
A semiconductor wafer-scale integrated-circuit as recited in claim 1, wherein each of said functional blocks comprises semiconductor memory cells as well as a configuration logic circuit.
References Cited (Backward Citations)
US4580259A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |