Patent US5033047A successfully refreshed from Google Patents.
US5033047A
Expired / Lapsed
US
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Multiprocessor system with a fault locator
Assignee: NEC Corp
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Filing: 1989-05-23
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Granted: 1991-07-16
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Expires: 2009-05-23
Abstract
Abstract In a multiprocessor system in which at least three processors are connected to a system bus by way of which data and source and destination processor identification numbers are exchanged between source and destination processors. A third processor receives the same data and the same source and destination processor ID numbers as those received by the destination processor. Each processor detects an error in data being transmitted to the bus and detects an error in data being received therefrom. A transmit error bit is stored into a transmit error bit register in response to the detection of error in the transmitted data and a receive error bit is stored into a receive error bit register in response to the detection of error in the received data. The processor ID numbers are also stored in registers in each processor in response to the detection of the errors. A fault locator is connected to the transmit and receive error bit registers of each processor and to the ID number registers of each processor to analyze the contents of such registers to locate a fault in the system on the basis of a majority decision.
Inventors
- 👤 Izushi Uehara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/079; G06F11/22
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
290 words
A multiprocessor system in which a plurality of processors are connected to a system bus of exchanging data and source and destination processor identification numbers between said processors, wherein each of said processors comprises: transmit and receive data registers coupled to said system bus for transmitting to and receiving data from said system bus; transmit parity check means coupled to said transmit data register for detecting an error in data being transmitted to said system bus for the transmit data register and receive parity check means coupled to said receive data register for detecting an error in data being received by said received data register from said system bus; transmit and receive error bit register means for storing a transmit error bit from said transmit parity check means in response to the detection of said error in said data being transmitted and storing a receive error bit from said receive parity check means in response to the detection of said error in said data being received; and source and destination processor number register means for storing the identification numbers of source and destination processors received from said system bus in response to the detection of said error in either of said data, wherein said multiprocessor system comprises fault locating means connected to the transmit and receive error bit register means of each of said processors and to the source and destination processor number register means of each of said processors for analyzing the contents of the transmit and receive error bit register means of each of said processors and the contents of the source and destination processor number register means of each of said processors and locating a fault in said system in accordance with the result of said analysis.
Claim 2
Dependent Claim
290 words
A multiprocessor system in which a plurality of processors are connected to a system bus of exchanging data and source and destination processor identification numbers between said processors, wherein each of said processors comprises: transmit and receive data registers coupled to said system bus for transmitting to and receiving data from said system bus; transmit parity check means coupled to said transmit data register for detecting an error in data being transmitted to said system bus for the transmit data register and receive parity check means coupled to said receive data register for detecting an error in data being received by said received data register from said system bus; transmit and receive error bit register means for storing a transmit error bit from said transmit parity check means in response to the detection of said error in said data being transmitted and storing a receive error bit from said receive parity check means in response to the detection of said error in said data being received; and source and destination processor number register means for storing the identification numbers of source and destination processors received from said system bus in response to the detection of said error in either of said data, wherein said multiprocessor system comprises fault locating means connected to the transmit and receive error bit register means of each of said processors and to the source and destination processor number register means of each of said processors for analyzing the contents of the transmit and receive error bit register means of each of said processors and the contents of the source and destination processor number register means of each of said processors and locating a fault in said system in accordance with the result of said analysis.
Claim 3
Dependent Claim
43 words
A multiprocessor system as claimed in claim 1, wherein said fault locating means includes majority decision means for analyzing the contents of the transmit and receive error bit register means of at least three of said processors on the basis of majority decision.
Claim 4
Dependent Claim
59 words
A multiprocessor system as claimed in claim 1, wherein said fault locating means determines that there is a faulty condition in said source processor by detecting the presence of said error bit in the transmit error bit register means of the source processor and in the receive error bit register means of said destination processor and a third processor.
Claim 5
Dependent Claim
63 words
A multiprocessor system as claimed in claim 3, wherein said fault locating means determines that there is a faulty condition in said destination processor by detecting the presence of said error bit in the receive error bit register means of said destination processor and by detecting the absence of said error bit in the receive error bit register means of said third processor.
Claim 6
Dependent Claim
63 words
A multiprocessor system as claimed in claim 3, wherein said fault locating means determines that there is a faulty condition in said third processor by detecting the presence of said error bit in the receive error bit register means of said third processor and by detecting the absence of said error bit in the receive error bit register means of said destination processor.
Claim 7
Dependent Claim
66 words
A multiprocessor system as claimed in claim 3, wherein said fault locating means determines that there is a faulty condition in said source processor by detecting the absence of said error bit in the transmit error bit register means of the source processor and detecting the presence of said error bit in the receive error bit register means of said destination processor and said third processor.
Claim 8
Dependent Claim
315 words
A multiprocessor system in which at least three processors are connected to a system bus for exchanging data and source and destination processor identification numbers between source and destination processors, wherein the other processor receives the same data and the same source and destination processor identification numbers as those received by said destination processor, wherein each of said processors comprises: transmit and receive data registers coupled to said system bus for transmitting to and receiving from said system bus; transmit parity check means coupled to said transmit data register for detecting an error in data being transmitted to said system bus from the transmit data register and receive parity check means coupled to said receive data register for detecting an error in data being receive by said receive data register from said system bus; transmit and receive error bit register means for storing a transmit error bit from said transmit parity check means in response to the detection of said error in said data being transmitted and storing a receive error bit from said received parity check means in response to the detection of said error in said data being received; and source and destination processor number register means for storing the identification numbers of source and destination processors received from said system bus in response to the detection of said error in either of said data, wherein said multiprocessor system comprises fault locating means connected to the transmit and receive error bit register means of each of said processors and to the source and destination processor number register means of each of said processors for analyzing the contents of the transmit and receive error bit register means of each of said processors and the contents of the source and destination processor number register means of each of said processors, and locating a fault in said system in accordance with the result of said analysis.
Claim 9
Dependent Claim
315 words
A multiprocessor system in which at least three processors are connected to a system bus for exchanging data and source and destination processor identification numbers between source and destination processors, wherein the other processor receives the same data and the same source and destination processor identification numbers as those received by said destination processor, wherein each of said processors comprises: transmit and receive data registers coupled to said system bus for transmitting to and receiving from said system bus; transmit parity check means coupled to said transmit data register for detecting an error in data being transmitted to said system bus from the transmit data register and receive parity check means coupled to said receive data register for detecting an error in data being receive by said receive data register from said system bus; transmit and receive error bit register means for storing a transmit error bit from said transmit parity check means in response to the detection of said error in said data being transmitted and storing a receive error bit from said received parity check means in response to the detection of said error in said data being received; and source and destination processor number register means for storing the identification numbers of source and destination processors received from said system bus in response to the detection of said error in either of said data, wherein said multiprocessor system comprises fault locating means connected to the transmit and receive error bit register means of each of said processors and to the source and destination processor number register means of each of said processors for analyzing the contents of the transmit and receive error bit register means of each of said processors and the contents of the source and destination processor number register means of each of said processors, and locating a fault in said system in accordance with the result of said analysis.
Claim 10
Dependent Claim
41 words
A multiprocessor system as claimed in claim 7, wherein said fault locating means includes majority decision means for analyzing the contents of the transmit and receive error bit register means of each of said processors on the basis of majority decision.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |